Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645171	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5248775

1

T1

13

T2

6

T3

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1557235	1			T1	27		T2	4		T3	88
values[0x0]	2005802	1			T1	10		T2	3		T3	19
values[0x1]	2330909	1			T1	13		T2	5		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320523	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5573423

1

T1

26

T2

9

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23259	1			T3	1		T4	7		T5	233
valid_sources[0x01]	22952	1			T5	278		T23	6		T34	172
valid_sources[0x02]	22622	1			T5	231		T36	1		T23	2
valid_sources[0x03]	24148	1			T5	248		T12	2		T27	1
valid_sources[0x04]	23585	1			T5	268		T23	3		T34	130
valid_sources[0x05]	22786	1			T1	1		T4	2		T5	254
valid_sources[0x06]	23843	1			T3	1		T4	1		T5	248
valid_sources[0x07]	25321	1			T3	3		T5	268		T36	1
valid_sources[0x08]	23762	1			T5	222		T23	9		T34	612
valid_sources[0x09]	22893	1			T3	1		T4	3		T5	261
valid_sources[0x0a]	24265	1			T3	1		T4	6		T5	284
valid_sources[0x0b]	22495	1			T2	3		T4	3		T5	226
valid_sources[0x0c]	23556	1			T3	2		T4	7		T5	256
valid_sources[0x0d]	24120	1			T4	6		T9	2		T5	230
valid_sources[0x0e]	23495	1			T5	245		T36	1		T34	505
valid_sources[0x0f]	23442	1			T9	1		T5	252		T12	5
valid_sources[0x10]	23142	1			T5	240		T59	6		T34	43
valid_sources[0x11]	24989	1			T3	1		T5	260		T27	1
valid_sources[0x12]	23685	1			T5	249		T23	4		T59	2
valid_sources[0x13]	22222	1			T3	1		T9	4		T5	243
valid_sources[0x14]	23010	1			T1	3		T3	1		T4	13
valid_sources[0x15]	22142	1			T3	1		T9	8		T5	232
valid_sources[0x16]	25173	1			T5	245		T36	1		T34	564
valid_sources[0x17]	24518	1			T9	2		T5	270		T36	1
valid_sources[0x18]	21885	1			T3	2		T4	5		T9	3
valid_sources[0x19]	23305	1			T1	6		T4	1		T5	274
valid_sources[0x1a]	23511	1			T4	2		T5	244		T11	1
valid_sources[0x1b]	22681	1			T5	233		T12	2		T23	4
valid_sources[0x1c]	24025	1			T3	1		T4	3		T9	4
valid_sources[0x1d]	21274	1			T4	1		T5	242		T36	1
valid_sources[0x1e]	23802	1			T5	260		T12	1		T23	1
valid_sources[0x1f]	23849	1			T5	235		T36	1		T59	3
valid_sources[0x20]	22955	1			T5	271		T36	2		T23	1
valid_sources[0x21]	23345	1			T3	1		T9	2		T5	274
valid_sources[0x22]	21802	1			T5	252		T23	1		T34	291
valid_sources[0x23]	26256	1			T3	1		T5	258		T60	1
valid_sources[0x24]	23830	1			T5	249		T12	2		T22	1
valid_sources[0x25]	27464	1			T5	256		T12	2		T23	3
valid_sources[0x26]	23295	1			T5	277		T23	3		T34	439
valid_sources[0x27]	22480	1			T5	257		T23	2		T59	3
valid_sources[0x28]	24675	1			T3	1		T5	267		T27	1
valid_sources[0x29]	22730	1			T1	4		T5	266		T36	1
valid_sources[0x2a]	23923	1			T3	1		T4	4		T5	217
valid_sources[0x2b]	23893	1			T5	246		T23	4		T34	180
valid_sources[0x2c]	23662	1			T3	1		T5	236		T12	12
valid_sources[0x2d]	21671	1			T4	2		T5	257		T23	11
valid_sources[0x2e]	23917	1			T5	263		T23	9		T34	377
valid_sources[0x2f]	20871	1			T4	5		T5	284		T11	3
valid_sources[0x30]	19203	1			T5	287		T12	1		T23	10
valid_sources[0x31]	24484	1			T5	272		T36	4		T34	180
valid_sources[0x32]	23429	1			T5	244		T11	1		T12	5
valid_sources[0x33]	23620	1			T1	1		T5	280		T36	1
valid_sources[0x34]	22960	1			T1	4		T5	235		T12	6
valid_sources[0x35]	23461	1			T9	2		T5	253		T22	1
valid_sources[0x36]	22222	1			T3	3		T4	2		T5	275
valid_sources[0x37]	22382	1			T5	272		T12	4		T34	211
valid_sources[0x38]	23443	1			T5	274		T60	2		T80	5
valid_sources[0x39]	22073	1			T3	1		T5	256		T36	1
valid_sources[0x3a]	25103	1			T4	4		T5	254		T34	635
valid_sources[0x3b]	21458	1			T3	2		T9	1		T5	271
valid_sources[0x3c]	21591	1			T5	233		T34	165		T37	1
valid_sources[0x3d]	24716	1			T9	4		T5	257		T36	1
valid_sources[0x3e]	22556	1			T3	1		T5	280		T36	1
valid_sources[0x3f]	24929	1			T3	1		T5	252		T12	2
valid_sources[0x40]	22583	1			T9	4		T5	266		T11	3
valid_sources[0x41]	24462	1			T5	244		T22	1		T23	3
valid_sources[0x42]	24547	1			T5	292		T36	1		T23	6
valid_sources[0x43]	22305	1			T4	8		T5	251		T36	2
valid_sources[0x44]	20972	1			T5	276		T36	1		T59	1
valid_sources[0x45]	22650	1			T2	1		T4	3		T5	263
valid_sources[0x46]	24009	1			T3	1		T5	256		T11	1
valid_sources[0x47]	23601	1			T5	255		T10	102		T34	485
valid_sources[0x48]	23648	1			T5	269		T50	1		T34	16
valid_sources[0x49]	22554	1			T4	4		T5	273		T36	1
valid_sources[0x4a]	20638	1			T9	1		T5	224		T11	3
valid_sources[0x4b]	24379	1			T4	7		T5	257		T12	9
valid_sources[0x4c]	24890	1			T3	1		T4	3		T5	261
valid_sources[0x4d]	21708	1			T5	269		T12	13		T22	1
valid_sources[0x4e]	21855	1			T1	2		T4	10		T5	282
valid_sources[0x4f]	22984	1			T1	1		T3	1		T4	1
valid_sources[0x50]	23587	1			T5	277		T12	1		T23	6
valid_sources[0x51]	22386	1			T4	3		T5	237		T36	1
valid_sources[0x52]	24903	1			T3	2		T5	261		T12	2
valid_sources[0x53]	22855	1			T3	2		T4	11		T5	265
valid_sources[0x54]	23239	1			T4	1		T5	256		T12	10
valid_sources[0x55]	22094	1			T5	249		T11	2		T27	2
valid_sources[0x56]	23211	1			T3	1		T4	5		T9	2
valid_sources[0x57]	20828	1			T3	1		T4	2		T9	1
valid_sources[0x58]	22870	1			T3	1		T5	253		T12	7
valid_sources[0x59]	22346	1			T3	1		T5	256		T23	6
valid_sources[0x5a]	24221	1			T3	1		T5	238		T36	1
valid_sources[0x5b]	24299	1			T4	5		T5	254		T11	6
valid_sources[0x5c]	23500	1			T3	2		T4	1		T5	255
valid_sources[0x5d]	26045	1			T4	2		T9	1		T5	243
valid_sources[0x5e]	23175	1			T3	1		T4	1		T5	271
valid_sources[0x5f]	22033	1			T5	239		T36	1		T23	1
valid_sources[0x60]	22481	1			T3	1		T5	268		T12	3
valid_sources[0x61]	23431	1			T5	266		T23	3		T34	163
valid_sources[0x62]	23315	1			T5	242		T36	1		T23	10
valid_sources[0x63]	22807	1			T5	249		T27	5		T23	1
valid_sources[0x64]	24291	1			T5	266		T36	1		T27	25
valid_sources[0x65]	22094	1			T3	1		T5	252		T34	423
valid_sources[0x66]	23871	1			T9	1		T5	258		T36	1
valid_sources[0x67]	24745	1			T9	2		T5	251		T12	1
valid_sources[0x68]	21982	1			T5	258		T11	1		T12	3
valid_sources[0x69]	22701	1			T1	2		T3	1		T5	257
valid_sources[0x6a]	22903	1			T4	5		T5	280		T12	5
valid_sources[0x6b]	22573	1			T3	1		T9	1		T5	278
valid_sources[0x6c]	23034	1			T3	1		T9	2		T5	266
valid_sources[0x6d]	23194	1			T5	294		T12	3		T27	4
valid_sources[0x6e]	23454	1			T4	4		T5	237		T12	1
valid_sources[0x6f]	22744	1			T3	1		T5	249		T36	1
valid_sources[0x70]	24075	1			T5	297		T36	1		T23	8
valid_sources[0x71]	22616	1			T3	1		T5	256		T12	3
valid_sources[0x72]	21941	1			T2	4		T3	2		T9	4
valid_sources[0x73]	24535	1			T5	256		T36	1		T34	315
valid_sources[0x74]	21365	1			T3	1		T5	248		T23	1
valid_sources[0x75]	23263	1			T4	1		T5	262		T36	1
valid_sources[0x76]	21439	1			T4	3		T5	257		T34	544
valid_sources[0x77]	23395	1			T3	2		T5	260		T34	539
valid_sources[0x78]	20977	1			T3	1		T5	275		T23	4
valid_sources[0x79]	21472	1			T4	3		T9	1		T5	257
valid_sources[0x7a]	23057	1			T5	229		T36	1		T23	1
valid_sources[0x7b]	22414	1			T5	283		T34	194		T61	4
valid_sources[0x7c]	21934	1			T9	2		T5	252		T23	10
valid_sources[0x7d]	24139	1			T5	271		T11	2		T36	1
valid_sources[0x7e]	21809	1			T3	1		T5	243		T12	3
valid_sources[0x7f]	24496	1			T5	238		T23	1		T59	1
valid_sources[0x80]	22407	1			T3	2		T5	251		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1323363

1

T1

5

T2

2

T3

6

values[0x0]

all_enables

biggest_size

1963108

1

T1

4

T2

3

T3

19

values[0x1]

all_enables

biggest_size

1962304

1

T1

4

T2

1

T3

17