Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2967 1 T3 1 T5 57 T10 1
non_zero_bins[1] 2005 1 T3 2 T9 3 T5 33
zero 9412 1 T1 5 T3 1 T9 1



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 508 1 T5 11 T23 2 T34 6
uni 3803 1 T3 1 T5 74 T12 1
gen 4586 1 T1 3 T3 1 T5 60
res 949 1 T3 1 T9 2 T5 12
ins 4538 1 T1 2 T3 1 T9 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 9427 1 T1 2 T3 3 T9 4
mubi_true 4957 1 T1 3 T3 1 T5 78



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 17 1 T27 1 T67 1 T280 1
pass 14367 1 T1 5 T3 4 T9 4



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 140 1 T5 2 T34 2 T35 1
upd non_zero_bins[0] pass mubi_true 101 1 T5 4 T23 1 T61 1
upd non_zero_bins[1] pass mubi_false 89 1 T5 2 T34 2 T40 1
upd non_zero_bins[1] pass mubi_true 84 1 T5 1 T23 1 T34 1
upd zero pass mubi_false 50 1 T5 1 T62 1 T80 1
upd zero pass mubi_true 44 1 T5 1 T34 1 T44 1
uni zero pass mubi_false 2808 1 T3 1 T5 52 T12 1
uni zero pass mubi_true 995 1 T5 22 T23 3 T34 12
gen non_zero_bins[0] pass mubi_false 548 1 T3 1 T5 11 T12 8
gen non_zero_bins[0] pass mubi_true 623 1 T5 12 T23 2 T59 1
gen non_zero_bins[1] pass mubi_false 395 1 T5 5 T23 2 T34 1
gen non_zero_bins[1] pass mubi_true 332 1 T5 5 T23 2 T34 2
gen zero fail mubi_false 16 1 T27 1 T67 1 T280 1
gen zero pass mubi_false 1927 1 T1 1 T5 26 T11 1
gen zero pass mubi_true 745 1 T1 2 T5 1 T11 2
res non_zero_bins[0] pass mubi_false 230 1 T5 3 T12 2 T36 1
res non_zero_bins[0] pass mubi_true 207 1 T5 2 T37 1 T80 1
res non_zero_bins[1] pass mubi_false 152 1 T9 2 T23 1 T42 1
res non_zero_bins[1] pass mubi_true 163 1 T3 1 T5 2 T23 1
res zero fail mubi_false 1 1 T220 1 - - - -
res zero pass mubi_false 105 1 T5 4 T10 1 T23 1
res zero pass mubi_true 91 1 T5 1 T23 2 T80 1
ins non_zero_bins[0] pass mubi_false 539 1 T5 11 T36 1 T23 2
ins non_zero_bins[0] pass mubi_true 579 1 T5 12 T10 1 T23 2
ins non_zero_bins[1] pass mubi_false 399 1 T3 1 T9 1 T5 10
ins non_zero_bins[1] pass mubi_true 391 1 T5 8 T12 1 T36 1
ins zero pass mubi_false 2028 1 T1 1 T9 1 T5 26
ins zero pass mubi_true 602 1 T1 1 T5 7 T11 2


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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