Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T66,T52
1	1	Covered	T1,T11,T22

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T36
1	1	Covered	T9,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T22
1	0	Covered	T2,T4,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T11,T22
1	Covered	T2,T4,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T11,T22
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T10

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T10,T12
AutoCaptGenCnt	143	Covered	T9,T10,T12
AutoCaptReseedCnt	141	Covered	T9,T10,T12
AutoDispatch	125	Covered	T9,T10,T12
AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns	69	Covered	T9,T10,T11
AutoSendGenCmd	150	Covered	T9,T10,T12
AutoSendReseedCmd	162	Covered	T9,T10,T12
BootDone	98	Covered	T1,T11,T27
BootGenAckWait	90	Covered	T1,T11,T27
BootInsAckWait	80	Covered	T1,T11,T22
BootLoadGen	85	Covered	T1,T11,T27
BootLoadIns	65	Covered	T1,T11,T22
BootLoadUni	102	Covered	T11,T27,T62
BootPulse	94	Covered	T1,T11,T27
BootUniAckWait	107	Covered	T11,T27,T62
Error	188	Covered	T2,T4,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T11,T22
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T12
AutoAckWait->Error	188	Covered	T104,T105,T106
AutoAckWait->Idle	211	Covered	T9,T10,T36
AutoAckWait->RejectCsrngEntropy	188	Covered	T27,T63,T81
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T10,T12
AutoCaptGenCnt->Error	188	Covered	T107,T108,T109
AutoCaptGenCnt->Idle	211	Covered	T9,T36,T110
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T111,T112,T113
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T12
AutoCaptReseedCnt->Error	188	Covered	T114
AutoCaptReseedCnt->Idle	211	Covered	T115,T116,T117
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T68,T118,T119
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T10,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T12
AutoDispatch->Error	188	Covered	T120,T121,T122
AutoDispatch->Idle	138	Covered	T12,T19,T97
AutoDispatch->RejectCsrngEntropy	188	Covered	T123,T124,T125
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T12
AutoFirstAckWait->Error	188	Covered	T126,T127
AutoFirstAckWait->Idle	211	Covered	T128,T129,T130
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T11,T131,T132
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns->Error	188	Covered	T133,T134,T135
AutoLoadIns->Idle	211	Covered	T43,T6,T63
AutoLoadIns->RejectCsrngEntropy	188	Covered	T75,T136,T137
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T10,T12
AutoSendGenCmd->Error	188	Covered	T138,T139,T140
AutoSendGenCmd->Idle	211	Covered	T78,T141,T142
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T143,T144,T99
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T10,T12
AutoSendReseedCmd->Error	188	Covered	T100,T145
AutoSendReseedCmd->Idle	211	Covered	T146,T147,T148
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T149,T150,T151
BootDone->BootLoadUni	102	Covered	T11,T27,T62
BootDone->Error	188	Covered	T52,T152,T153
BootDone->Idle	211	Covered	T66,T154,T155
BootDone->RejectCsrngEntropy	188	Covered	T1,T156,T157
BootGenAckWait->BootPulse	94	Covered	T1,T11,T27
BootGenAckWait->Error	188	Covered	T158,T159
BootGenAckWait->Idle	211	Covered	T52,T160,T161
BootGenAckWait->RejectCsrngEntropy	188	Covered	T43,T84,T162
BootInsAckWait->BootLoadGen	85	Covered	T1,T11,T27
BootInsAckWait->Error	188	Covered	T54,T163,T164
BootInsAckWait->Idle	211	Covered	T91,T54,T165
BootInsAckWait->RejectCsrngEntropy	188	Covered	T22,T49,T39
BootLoadGen->BootGenAckWait	90	Covered	T1,T11,T27
BootLoadGen->Error	188	Covered	T166
BootLoadGen->Idle	211	Covered	T167,T168,T169
BootLoadGen->RejectCsrngEntropy	188	Covered	T170,T171,T172
BootLoadIns->BootInsAckWait	80	Covered	T1,T11,T22
BootLoadIns->Error	188	Covered	T173,T174,T175
BootLoadIns->Idle	211	Covered	T176,T177,T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T179,T180,T181
BootLoadUni->BootUniAckWait	107	Covered	T11,T27,T62
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T182,T183
BootPulse->BootDone	98	Covered	T1,T11,T27
BootPulse->Error	188	Covered	T184,T185
BootPulse->Idle	211	Covered	T186,T187,T188
BootPulse->RejectCsrngEntropy	188	Covered	T189,T190,T191
BootUniAckWait->Error	188	Covered	T192
BootUniAckWait->Idle	112	Covered	T11,T27,T62
BootUniAckWait->RejectCsrngEntropy	188	Covered	T193,T194,T195
Idle->AutoLoadIns	69	Covered	T9,T10,T11
Idle->BootLoadIns	65	Covered	T1,T11,T22
Idle->Error	188	Covered	T4,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T1,T11,T22
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T196,T197,T198
RejectCsrngEntropy->Idle	211	Covered	T1,T11,T22
SWPortMode->Error	188	Covered	T4,T15,T16
SWPortMode->Idle	211	Covered	T1,T4,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T27,T43,T49

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T22
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T22
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T22
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T22
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T27
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T27
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T27
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T27
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T27,T62
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T11,T27
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T27,T62
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T62,T37,T199
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T11,T27,T62
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T12,T19,T97
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T10,T12
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T12
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T22
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T4,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T11,T22
0	-	-	1	Covered	T1,T9,T10
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	227424630	162141	0	0
FpvSecCmErrorStEscalate_A	227424630	163442	0	0
u_state_regs_A	227383408	227181584	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	162141	0	0
T2	1742	1030	0	0
T3	4690	0	0	0
T4	25005	8850	0	0
T5	249098	0	0	0
T6	0	1050	0	0
T7	0	207	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1068	0	0
T16	0	462	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	394	0	0
T64	0	560	0	0
T65	0	1088	0	0
T66	0	1071	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	163442	0	0
T2	1742	1031	0	0
T3	4690	0	0	0
T4	25005	8980	0	0
T5	249098	0	0	0
T6	0	1051	0	0
T7	0	208	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1069	0	0
T16	0	463	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	395	0	0
T64	0	561	0	0
T65	0	1089	0	0
T66	0	1072	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227383408	227181584	0	0
T1	1845	1762	0	0
T2	1624	1488	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0