Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T32
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T29,T33
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454065372	599236	0	0
DepthKnown_A	454849260	454445612	0	0
RvalidKnown_A	454849260	454445612	0	0
WreadyKnown_A	454849260	454445612	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	454446580	692984	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454065372	599236	0	0
T5	498196	0	0	0
T6	0	160	0	0
T9	4746	3631	0	0
T10	2738	2062	0	0
T11	3562	300	0	0
T12	4090	1479	0	0
T22	3312	0	0	0
T23	66056	0	0	0
T27	4806	478	0	0
T36	4394	2762	0	0
T39	0	367	0	0
T43	0	329	0	0
T59	2882	0	0	0
T63	0	933	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454849260	454445612	0	0
T1	3690	3524	0	0
T2	3484	3212	0	0
T3	9380	9238	0	0
T4	50010	29046	0	0
T5	498196	498170	0	0
T9	4746	4578	0	0
T10	2738	2602	0	0
T11	3562	3448	0	0
T12	4090	3932	0	0
T22	3312	3180	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454849260	454445612	0	0
T1	3690	3524	0	0
T2	3484	3212	0	0
T3	9380	9238	0	0
T4	50010	29046	0	0
T5	498196	498170	0	0
T9	4746	4578	0	0
T10	2738	2602	0	0
T11	3562	3448	0	0
T12	4090	3932	0	0
T22	3312	3180	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454849260	454445612	0	0
T1	3690	3524	0	0
T2	3484	3212	0	0
T3	9380	9238	0	0
T4	50010	29046	0	0
T5	498196	498170	0	0
T9	4746	4578	0	0
T10	2738	2602	0	0
T11	3562	3448	0	0
T12	4090	3932	0	0
T22	3312	3180	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	454446580	692984	0	0
T2	3484	220	0	0
T3	9380	0	0	0
T4	1896	0	0	0
T5	498196	0	0	0
T6	0	1606	0	0
T9	4746	3631	0	0
T10	2738	2062	0	0
T11	3562	300	0	0
T12	4090	1479	0	0
T22	3312	0	0	0
T27	0	478	0	0
T36	4394	2762	0	0
T43	0	329	0	0
T64	0	340	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T84,T8,T85
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T33,T86
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	227032686	294140	0	0
DepthKnown_A	227424630	227222806	0	0
RvalidKnown_A	227424630	227222806	0	0
WreadyKnown_A	227424630	227222806	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	227223290	340791	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227032686	294140	0	0
T5	249098	0	0	0
T6	0	29	0	0
T9	2373	1754	0	0
T10	1369	1014	0	0
T11	1781	151	0	0
T12	2045	730	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	241	0	0
T36	2197	1362	0	0
T39	0	171	0	0
T43	0	147	0	0
T59	1441	0	0	0
T63	0	427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	227223290	340791	0	0
T2	1742	111	0	0
T3	4690	0	0	0
T4	948	0	0	0
T5	249098	0	0	0
T6	0	742	0	0
T9	2373	1754	0	0
T10	1369	1014	0	0
T11	1781	151	0	0
T12	2045	730	0	0
T22	1656	0	0	0
T27	0	241	0	0
T36	2197	1362	0	0
T43	0	147	0	0
T64	0	171	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T32
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T87,T88
1	0	1	Covered	T2,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	227032686	305096	0	0
DepthKnown_A	227424630	227222806	0	0
RvalidKnown_A	227424630	227222806	0	0
WreadyKnown_A	227424630	227222806	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	227223290	352193	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227032686	305096	0	0
T5	249098	0	0	0
T6	0	131	0	0
T9	2373	1877	0	0
T10	1369	1048	0	0
T11	1781	149	0	0
T12	2045	749	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	237	0	0
T36	2197	1400	0	0
T39	0	196	0	0
T43	0	182	0	0
T59	1441	0	0	0
T63	0	506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	227223290	352193	0	0
T2	1742	109	0	0
T3	4690	0	0	0
T4	948	0	0	0
T5	249098	0	0	0
T6	0	864	0	0
T9	2373	1877	0	0
T10	1369	1048	0	0
T11	1781	149	0	0
T12	2045	749	0	0
T22	1656	0	0	0
T27	0	237	0	0
T36	2197	1400	0	0
T43	0	182	0	0
T64	0	169	0	0