Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T9 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T9 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T10 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T9 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T10,T36 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T3,T9 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T5 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T5 |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T10,T81 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T9,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T3,T9 |
| 0 |
0 |
1 |
Covered |
T1,T9,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T9,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1819397040 |
207986105 |
0 |
7720 |
| T1 |
3690 |
1110 |
0 |
2 |
| T2 |
3484 |
0 |
0 |
2 |
| T3 |
9380 |
0 |
0 |
2 |
| T4 |
50010 |
0 |
0 |
2 |
| T5 |
747294 |
244137 |
0 |
3 |
| T9 |
7119 |
734 |
0 |
3 |
| T10 |
4107 |
733 |
0 |
3 |
| T11 |
5343 |
0 |
0 |
3 |
| T12 |
8180 |
2176 |
0 |
4 |
| T22 |
6624 |
944 |
0 |
4 |
| T23 |
66056 |
4929 |
0 |
2 |
| T27 |
4806 |
1425 |
0 |
2 |
| T34 |
301543 |
234530 |
0 |
1 |
| T36 |
4394 |
835 |
0 |
2 |
| T37 |
4538 |
4391 |
0 |
1 |
| T38 |
2061 |
0 |
0 |
1 |
| T40 |
0 |
6175 |
0 |
0 |
| T41 |
0 |
2159 |
0 |
0 |
| T42 |
0 |
2442 |
0 |
0 |
| T44 |
0 |
2091 |
0 |
0 |
| T46 |
0 |
2652 |
0 |
0 |
| T50 |
1078 |
0 |
0 |
1 |
| T59 |
2882 |
1071 |
0 |
2 |
| T60 |
1598 |
1139 |
0 |
1 |
| T61 |
21483 |
10424 |
0 |
1 |
| T64 |
1116 |
0 |
0 |
1 |
| T67 |
0 |
1130 |
0 |
0 |
| T68 |
0 |
117 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1819397040 |
207986105 |
0 |
0 |
| T1 |
3690 |
1110 |
0 |
0 |
| T2 |
3484 |
0 |
0 |
0 |
| T3 |
9380 |
0 |
0 |
0 |
| T4 |
50010 |
0 |
0 |
0 |
| T5 |
747294 |
244137 |
0 |
0 |
| T9 |
7119 |
734 |
0 |
0 |
| T10 |
4107 |
733 |
0 |
0 |
| T11 |
5343 |
0 |
0 |
0 |
| T12 |
8180 |
2176 |
0 |
0 |
| T22 |
6624 |
944 |
0 |
0 |
| T23 |
66056 |
4929 |
0 |
0 |
| T27 |
4806 |
1425 |
0 |
0 |
| T34 |
301543 |
234530 |
0 |
0 |
| T36 |
4394 |
835 |
0 |
0 |
| T37 |
4538 |
4391 |
0 |
0 |
| T38 |
2061 |
0 |
0 |
0 |
| T40 |
0 |
6175 |
0 |
0 |
| T41 |
0 |
2159 |
0 |
0 |
| T42 |
0 |
2442 |
0 |
0 |
| T44 |
0 |
2091 |
0 |
0 |
| T46 |
0 |
2652 |
0 |
0 |
| T50 |
1078 |
0 |
0 |
0 |
| T59 |
2882 |
1071 |
0 |
0 |
| T60 |
1598 |
1139 |
0 |
0 |
| T61 |
21483 |
10424 |
0 |
0 |
| T64 |
1116 |
0 |
0 |
0 |
| T67 |
0 |
1130 |
0 |
0 |
| T68 |
0 |
117 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T9 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T9 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T10 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T9 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T9 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T10,T36 |
| 1 | 1 | Covered | T1,T3,T9 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T3,T9 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
12 |
85.71 |
| TERNARY |
142 |
4 |
3 |
75.00 |
| TERNARY |
147 |
3 |
2 |
66.67 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T3,T9 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T9 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
81629 |
0 |
965 |
| T1 |
1845 |
53 |
0 |
1 |
| T2 |
1742 |
0 |
0 |
1 |
| T3 |
4690 |
0 |
0 |
1 |
| T4 |
25005 |
0 |
0 |
1 |
| T5 |
249098 |
0 |
0 |
1 |
| T9 |
2373 |
490 |
0 |
1 |
| T10 |
1369 |
409 |
0 |
1 |
| T11 |
1781 |
0 |
0 |
1 |
| T12 |
2045 |
35 |
0 |
1 |
| T22 |
1656 |
5 |
0 |
1 |
| T36 |
0 |
699 |
0 |
0 |
| T43 |
0 |
122 |
0 |
0 |
| T49 |
0 |
69 |
0 |
0 |
| T59 |
0 |
54 |
0 |
0 |
| T62 |
0 |
35 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
81629 |
0 |
0 |
| T1 |
1845 |
53 |
0 |
0 |
| T2 |
1742 |
0 |
0 |
0 |
| T3 |
4690 |
0 |
0 |
0 |
| T4 |
25005 |
0 |
0 |
0 |
| T5 |
249098 |
0 |
0 |
0 |
| T9 |
2373 |
490 |
0 |
0 |
| T10 |
1369 |
409 |
0 |
0 |
| T11 |
1781 |
0 |
0 |
0 |
| T12 |
2045 |
35 |
0 |
0 |
| T22 |
1656 |
5 |
0 |
0 |
| T36 |
0 |
699 |
0 |
0 |
| T43 |
0 |
122 |
0 |
0 |
| T49 |
0 |
69 |
0 |
0 |
| T59 |
0 |
54 |
0 |
0 |
| T62 |
0 |
35 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T9,T5 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T5 |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T9,T5 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T9,T5 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T81,T186 |
| 1 | 1 | Covered | T1,T9,T5 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T9,T5 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T9,T5 |
| 0 |
0 |
1 |
Covered |
T1,T9,T5 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T9,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T9,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
206503200 |
0 |
965 |
| T1 |
1845 |
111 |
0 |
1 |
| T2 |
1742 |
0 |
0 |
1 |
| T3 |
4690 |
0 |
0 |
1 |
| T4 |
25005 |
0 |
0 |
1 |
| T5 |
249098 |
244137 |
0 |
1 |
| T9 |
2373 |
734 |
0 |
1 |
| T10 |
1369 |
0 |
0 |
1 |
| T11 |
1781 |
0 |
0 |
1 |
| T12 |
2045 |
1045 |
0 |
1 |
| T22 |
1656 |
0 |
0 |
1 |
| T23 |
0 |
4929 |
0 |
0 |
| T27 |
0 |
1425 |
0 |
0 |
| T34 |
0 |
234530 |
0 |
0 |
| T59 |
0 |
1071 |
0 |
0 |
| T60 |
0 |
1139 |
0 |
0 |
| T61 |
0 |
10424 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
206503200 |
0 |
0 |
| T1 |
1845 |
111 |
0 |
0 |
| T2 |
1742 |
0 |
0 |
0 |
| T3 |
4690 |
0 |
0 |
0 |
| T4 |
25005 |
0 |
0 |
0 |
| T5 |
249098 |
244137 |
0 |
0 |
| T9 |
2373 |
734 |
0 |
0 |
| T10 |
1369 |
0 |
0 |
0 |
| T11 |
1781 |
0 |
0 |
0 |
| T12 |
2045 |
1045 |
0 |
0 |
| T22 |
1656 |
0 |
0 |
0 |
| T23 |
0 |
4929 |
0 |
0 |
| T27 |
0 |
1425 |
0 |
0 |
| T34 |
0 |
234530 |
0 |
0 |
| T59 |
0 |
1071 |
0 |
0 |
| T60 |
0 |
1139 |
0 |
0 |
| T61 |
0 |
10424 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T12,T36,T37 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T36,T37 |
| 1 | 0 | Covered | T12,T36,T37 |
| 1 | 1 | Covered | T12,T36,T37 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T36,T37 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T12,T36,T37 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T12,T36,T37 |
| 1 | 1 | Covered | T12,T36,T37 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T36,T37 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T36,T37 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T36,T37 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T36,T37 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T36,T37 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T68,T214,T191 |
| 1 | 1 | Covered | T12,T36,T37 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T36,T37 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T12,T36,T37 |
| 0 |
0 |
1 |
Covered |
T12,T36,T37 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T36,T37 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T36,T37 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
280121 |
0 |
965 |
| T12 |
2045 |
1131 |
0 |
1 |
| T22 |
1656 |
0 |
0 |
1 |
| T23 |
33028 |
0 |
0 |
1 |
| T27 |
2403 |
0 |
0 |
1 |
| T34 |
301543 |
0 |
0 |
1 |
| T36 |
2197 |
835 |
0 |
1 |
| T37 |
0 |
4391 |
0 |
0 |
| T40 |
0 |
3414 |
0 |
0 |
| T41 |
0 |
1089 |
0 |
0 |
| T42 |
0 |
2442 |
0 |
0 |
| T44 |
0 |
1227 |
0 |
0 |
| T46 |
0 |
2652 |
0 |
0 |
| T50 |
1078 |
0 |
0 |
1 |
| T59 |
1441 |
0 |
0 |
1 |
| T60 |
1598 |
0 |
0 |
1 |
| T61 |
21483 |
0 |
0 |
1 |
| T67 |
0 |
1130 |
0 |
0 |
| T68 |
0 |
117 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
280121 |
0 |
0 |
| T12 |
2045 |
1131 |
0 |
0 |
| T22 |
1656 |
0 |
0 |
0 |
| T23 |
33028 |
0 |
0 |
0 |
| T27 |
2403 |
0 |
0 |
0 |
| T34 |
301543 |
0 |
0 |
0 |
| T36 |
2197 |
835 |
0 |
0 |
| T37 |
0 |
4391 |
0 |
0 |
| T40 |
0 |
3414 |
0 |
0 |
| T41 |
0 |
1089 |
0 |
0 |
| T42 |
0 |
2442 |
0 |
0 |
| T44 |
0 |
1227 |
0 |
0 |
| T46 |
0 |
2652 |
0 |
0 |
| T50 |
1078 |
0 |
0 |
0 |
| T59 |
1441 |
0 |
0 |
0 |
| T60 |
1598 |
0 |
0 |
0 |
| T61 |
21483 |
0 |
0 |
0 |
| T67 |
0 |
1130 |
0 |
0 |
| T68 |
0 |
117 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T22,T43 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T22,T43 |
| 1 | 0 | Covered | T1,T10,T22 |
| 1 | 1 | Covered | T1,T22,T43 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T22,T43 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T10,T22 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T10,T22 |
| 1 | 1 | Covered | T1,T10,T22 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T22 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T22 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T22 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T22 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T10,T22 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T215,T216 |
| 1 | 1 | Covered | T1,T10,T22 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T10,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T10,T22 |
| 0 |
0 |
1 |
Covered |
T1,T10,T22 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T10,T22 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T10,T22 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
285504 |
0 |
965 |
| T1 |
1845 |
999 |
0 |
1 |
| T2 |
1742 |
0 |
0 |
1 |
| T3 |
4690 |
0 |
0 |
1 |
| T4 |
25005 |
0 |
0 |
1 |
| T5 |
249098 |
0 |
0 |
1 |
| T9 |
2373 |
0 |
0 |
1 |
| T10 |
1369 |
733 |
0 |
1 |
| T11 |
1781 |
0 |
0 |
1 |
| T12 |
2045 |
0 |
0 |
1 |
| T22 |
1656 |
944 |
0 |
1 |
| T40 |
0 |
2761 |
0 |
0 |
| T41 |
0 |
1070 |
0 |
0 |
| T43 |
0 |
1285 |
0 |
0 |
| T44 |
0 |
864 |
0 |
0 |
| T51 |
0 |
415 |
0 |
0 |
| T71 |
0 |
2414 |
0 |
0 |
| T72 |
0 |
363 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
285504 |
0 |
0 |
| T1 |
1845 |
999 |
0 |
0 |
| T2 |
1742 |
0 |
0 |
0 |
| T3 |
4690 |
0 |
0 |
0 |
| T4 |
25005 |
0 |
0 |
0 |
| T5 |
249098 |
0 |
0 |
0 |
| T9 |
2373 |
0 |
0 |
0 |
| T10 |
1369 |
733 |
0 |
0 |
| T11 |
1781 |
0 |
0 |
0 |
| T12 |
2045 |
0 |
0 |
0 |
| T22 |
1656 |
944 |
0 |
0 |
| T40 |
0 |
2761 |
0 |
0 |
| T41 |
0 |
1070 |
0 |
0 |
| T43 |
0 |
1285 |
0 |
0 |
| T44 |
0 |
864 |
0 |
0 |
| T51 |
0 |
415 |
0 |
0 |
| T71 |
0 |
2414 |
0 |
0 |
| T72 |
0 |
363 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T44,T45 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T10,T44,T45 |
| 1 | 0 | Covered | T9,T10,T36 |
| 1 | 1 | Covered | T10,T44,T45 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T44,T45 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T9,T10,T36 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T9,T10,T36 |
| 1 | 1 | Covered | T9,T10,T36 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T10,T36 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T10,T36 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T10,T36 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T10,T36 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T9,T10,T36 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T154,T217,T183 |
| 1 | 1 | Covered | T9,T10,T36 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9,T10,T36 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T9,T10,T36 |
| 0 |
0 |
1 |
Covered |
T9,T10,T36 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T9,T10,T36 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T9,T10,T36 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
234647 |
0 |
965 |
| T5 |
249098 |
0 |
0 |
1 |
| T9 |
2373 |
766 |
0 |
1 |
| T10 |
1369 |
539 |
0 |
1 |
| T11 |
1781 |
0 |
0 |
1 |
| T12 |
2045 |
0 |
0 |
1 |
| T22 |
1656 |
0 |
0 |
1 |
| T23 |
33028 |
0 |
0 |
1 |
| T27 |
2403 |
0 |
0 |
1 |
| T28 |
0 |
746 |
0 |
0 |
| T36 |
2197 |
857 |
0 |
1 |
| T40 |
0 |
3002 |
0 |
0 |
| T41 |
0 |
1557 |
0 |
0 |
| T42 |
0 |
2440 |
0 |
0 |
| T44 |
0 |
1208 |
0 |
0 |
| T45 |
0 |
1297 |
0 |
0 |
| T46 |
0 |
2129 |
0 |
0 |
| T59 |
1441 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
234647 |
0 |
0 |
| T5 |
249098 |
0 |
0 |
0 |
| T9 |
2373 |
766 |
0 |
0 |
| T10 |
1369 |
539 |
0 |
0 |
| T11 |
1781 |
0 |
0 |
0 |
| T12 |
2045 |
0 |
0 |
0 |
| T22 |
1656 |
0 |
0 |
0 |
| T23 |
33028 |
0 |
0 |
0 |
| T27 |
2403 |
0 |
0 |
0 |
| T28 |
0 |
746 |
0 |
0 |
| T36 |
2197 |
857 |
0 |
0 |
| T40 |
0 |
3002 |
0 |
0 |
| T41 |
0 |
1557 |
0 |
0 |
| T42 |
0 |
2440 |
0 |
0 |
| T44 |
0 |
1208 |
0 |
0 |
| T45 |
0 |
1297 |
0 |
0 |
| T46 |
0 |
2129 |
0 |
0 |
| T59 |
1441 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T39,T19 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T19 |
| 1 | 0 | Covered | T38,T39,T19 |
| 1 | 1 | Covered | T38,T39,T19 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T19 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T38,T39,T19 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T38,T39,T19 |
| 1 | 1 | Covered | T38,T39,T19 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T19 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T19 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T19 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T19 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T19 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T155,T218,T182 |
| 1 | 1 | Covered | T38,T39,T19 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T19 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T38,T39,T19 |
| 0 |
0 |
1 |
Covered |
T38,T39,T19 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T38,T39,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T38,T39,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
231782 |
0 |
965 |
| T16 |
834 |
0 |
0 |
1 |
| T19 |
1608 |
837 |
0 |
1 |
| T37 |
4538 |
0 |
0 |
1 |
| T38 |
2061 |
1340 |
0 |
1 |
| T39 |
2606 |
1436 |
0 |
1 |
| T40 |
0 |
3455 |
0 |
0 |
| T41 |
0 |
1178 |
0 |
0 |
| T42 |
0 |
2427 |
0 |
0 |
| T46 |
0 |
2072 |
0 |
0 |
| T51 |
1045 |
0 |
0 |
1 |
| T53 |
0 |
723 |
0 |
0 |
| T63 |
2779 |
0 |
0 |
1 |
| T64 |
1116 |
0 |
0 |
1 |
| T65 |
2008 |
0 |
0 |
1 |
| T73 |
0 |
2156 |
0 |
0 |
| T75 |
0 |
1390 |
0 |
0 |
| T76 |
934 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
231782 |
0 |
0 |
| T16 |
834 |
0 |
0 |
0 |
| T19 |
1608 |
837 |
0 |
0 |
| T37 |
4538 |
0 |
0 |
0 |
| T38 |
2061 |
1340 |
0 |
0 |
| T39 |
2606 |
1436 |
0 |
0 |
| T40 |
0 |
3455 |
0 |
0 |
| T41 |
0 |
1178 |
0 |
0 |
| T42 |
0 |
2427 |
0 |
0 |
| T46 |
0 |
2072 |
0 |
0 |
| T51 |
1045 |
0 |
0 |
0 |
| T53 |
0 |
723 |
0 |
0 |
| T63 |
2779 |
0 |
0 |
0 |
| T64 |
1116 |
0 |
0 |
0 |
| T65 |
2008 |
0 |
0 |
0 |
| T73 |
0 |
2156 |
0 |
0 |
| T75 |
0 |
1390 |
0 |
0 |
| T76 |
934 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T11,T38 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T11,T38 |
| 1 | 0 | Covered | T3,T11,T38 |
| 1 | 1 | Covered | T3,T11,T38 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T38 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T11,T38 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T3,T11,T38 |
| 1 | 1 | Covered | T3,T11,T38 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T38 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T38 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T38 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T11,T38 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T11,T38 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T219,T220,T221 |
| 1 | 1 | Covered | T3,T11,T38 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T11,T38 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T3,T11,T38 |
| 0 |
0 |
1 |
Covered |
T3,T11,T38 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T11,T38 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T11,T38 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
202778 |
0 |
965 |
| T3 |
4690 |
2382 |
0 |
1 |
| T4 |
25005 |
0 |
0 |
1 |
| T5 |
249098 |
0 |
0 |
1 |
| T9 |
2373 |
0 |
0 |
1 |
| T10 |
1369 |
0 |
0 |
1 |
| T11 |
1781 |
1094 |
0 |
1 |
| T12 |
2045 |
0 |
0 |
1 |
| T21 |
0 |
2403 |
0 |
0 |
| T22 |
1656 |
0 |
0 |
1 |
| T27 |
2403 |
0 |
0 |
1 |
| T36 |
2197 |
0 |
0 |
1 |
| T38 |
0 |
1366 |
0 |
0 |
| T40 |
0 |
2650 |
0 |
0 |
| T41 |
0 |
1527 |
0 |
0 |
| T42 |
0 |
2271 |
0 |
0 |
| T44 |
0 |
1189 |
0 |
0 |
| T46 |
0 |
2086 |
0 |
0 |
| T73 |
0 |
1641 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
202778 |
0 |
0 |
| T3 |
4690 |
2382 |
0 |
0 |
| T4 |
25005 |
0 |
0 |
0 |
| T5 |
249098 |
0 |
0 |
0 |
| T9 |
2373 |
0 |
0 |
0 |
| T10 |
1369 |
0 |
0 |
0 |
| T11 |
1781 |
1094 |
0 |
0 |
| T12 |
2045 |
0 |
0 |
0 |
| T21 |
0 |
2403 |
0 |
0 |
| T22 |
1656 |
0 |
0 |
0 |
| T27 |
2403 |
0 |
0 |
0 |
| T36 |
2197 |
0 |
0 |
0 |
| T38 |
0 |
1366 |
0 |
0 |
| T40 |
0 |
2650 |
0 |
0 |
| T41 |
0 |
1527 |
0 |
0 |
| T42 |
0 |
2271 |
0 |
0 |
| T44 |
0 |
1189 |
0 |
0 |
| T46 |
0 |
2086 |
0 |
0 |
| T73 |
0 |
1641 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T19,T40,T41 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T40,T41 |
| 1 | 0 | Covered | T19,T40,T41 |
| 1 | 1 | Covered | T19,T40,T41 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T40,T41 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T19,T40,T41 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T19,T40,T41 |
| 1 | 1 | Covered | T19,T40,T41 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T40,T41 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T40,T41 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T40,T41 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T19,T40,T41 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T19,T40,T41 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T161,T187 |
| 1 | 1 | Covered | T19,T40,T41 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T19,T40,T41 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T19,T40,T41 |
| 0 |
0 |
1 |
Covered |
T19,T40,T41 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T19,T40,T41 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T19,T40,T41 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
166444 |
0 |
965 |
| T7 |
2243 |
0 |
0 |
1 |
| T19 |
1608 |
855 |
0 |
1 |
| T21 |
0 |
2340 |
0 |
0 |
| T28 |
1616 |
0 |
0 |
1 |
| T29 |
1992 |
0 |
0 |
1 |
| T40 |
0 |
2704 |
0 |
0 |
| T41 |
0 |
1504 |
0 |
0 |
| T44 |
1787 |
0 |
0 |
1 |
| T46 |
0 |
2584 |
0 |
0 |
| T48 |
0 |
6819 |
0 |
0 |
| T52 |
2981 |
0 |
0 |
1 |
| T66 |
2973 |
0 |
0 |
1 |
| T73 |
0 |
1578 |
0 |
0 |
| T77 |
0 |
1889 |
0 |
0 |
| T78 |
0 |
1203 |
0 |
0 |
| T79 |
0 |
1269 |
0 |
0 |
| T80 |
24670 |
0 |
0 |
1 |
| T81 |
3406 |
0 |
0 |
1 |
| T82 |
1013 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
227424630 |
166444 |
0 |
0 |
| T7 |
2243 |
0 |
0 |
0 |
| T19 |
1608 |
855 |
0 |
0 |
| T21 |
0 |
2340 |
0 |
0 |
| T28 |
1616 |
0 |
0 |
0 |
| T29 |
1992 |
0 |
0 |
0 |
| T40 |
0 |
2704 |
0 |
0 |
| T41 |
0 |
1504 |
0 |
0 |
| T44 |
1787 |
0 |
0 |
0 |
| T46 |
0 |
2584 |
0 |
0 |
| T48 |
0 |
6819 |
0 |
0 |
| T52 |
2981 |
0 |
0 |
0 |
| T66 |
2973 |
0 |
0 |
0 |
| T73 |
0 |
1578 |
0 |
0 |
| T77 |
0 |
1889 |
0 |
0 |
| T78 |
0 |
1203 |
0 |
0 |
| T79 |
0 |
1269 |
0 |
0 |
| T80 |
24670 |
0 |
0 |
0 |
| T81 |
3406 |
0 |
0 |
0 |
| T82 |
1013 |
0 |
0 |
0 |