Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	135	1			T30	1		T46	1		T84	1
auto_req_mode	144	1			T1	1		T10	1		T21	1
sw_mode	2973	1			T2	20		T3	1		T23	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

297

1

T1

1

T3

1

T23

1

single

102

1

T76

1

T11

1

T40

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1228	1			T23	1		T10	1		T76	1
auto[2]	120	1			T236	1		T286	1		T287	8
auto[3]	89	1			T2	20		T82	1		T288	1
auto[4]	131	1			T58	1		T106	1		T289	1
auto[5]	32	1			T30	1		T11	1		T41	1
auto[6]	106	1			T1	1		T290	1		T291	78
auto[7]	1546	1			T3	1		T21	1		T48	5

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	79	1			T46	1		T84	1		T104	1
auto[1]	auto_req_mode	88	1			T10	1		T22	1		T77	1
auto[1]	sw_mode	1061	1			T23	1		T76	1		T5	103
auto[2]	auto_req_mode	4	1			T236	1		T286	1		T292	1
auto[2]	sw_mode	116	1			T287	8		T224	51		T293	1
auto[3]	boot_req_mode	6	1			T82	1		T288	1		T294	1
auto[3]	auto_req_mode	2	1			T295	1		T296	1		-	-
auto[3]	sw_mode	81	1			T2	20		T297	1		T298	4
auto[4]	boot_req_mode	1	1			T106	1		-	-		-	-
auto[4]	auto_req_mode	5	1			T58	1		T289	1		T299	1
auto[4]	sw_mode	125	1			T222	29		T225	85		T300	1
auto[5]	boot_req_mode	4	1			T30	1		T301	1		T302	1
auto[5]	auto_req_mode	5	1			T11	1		T41	1		T303	1
auto[5]	sw_mode	23	1			T64	12		T304	1		T305	1
auto[6]	boot_req_mode	5	1			T290	1		T306	1		T307	1
auto[6]	auto_req_mode	1	1			T1	1		-	-		-	-
auto[6]	sw_mode	100	1			T291	78		T308	21		T309	1
auto[7]	boot_req_mode	40	1			T42	1		T59	1		T310	1
auto[7]	auto_req_mode	39	1			T21	1		T39	1		T12	1
auto[7]	sw_mode	1467	1			T3	1		T48	5		T86	1