Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	709550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5704365

1

T1

40

T2

31492

T3

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1694802	1			T1	82		T2	8993		T3	324
values[0x0]	2180712	1			T1	22		T2	12072		T3	21
values[0x1]	2538401	1			T1	21		T2	13591		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349396	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6064519

1

T1

61

T2

33170

T3

160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24656	1			T2	479		T3	11		T5	1192
valid_sources[0x01]	23430	1			T2	173		T3	3		T5	1342
valid_sources[0x02]	22730	1			T2	226		T75	1		T5	1227
valid_sources[0x03]	23974	1			T1	7		T2	301		T3	4
valid_sources[0x04]	25806	1			T2	6		T23	10		T5	1272
valid_sources[0x05]	25291	1			T2	18		T18	1		T5	1163
valid_sources[0x06]	23541	1			T2	19		T10	1		T5	1322
valid_sources[0x07]	24573	1			T2	82		T3	4		T10	3
valid_sources[0x08]	25450	1			T2	260		T10	5		T5	1379
valid_sources[0x09]	26769	1			T2	117		T5	1337		T21	1
valid_sources[0x0a]	24391	1			T2	76		T18	2		T10	1
valid_sources[0x0b]	23837	1			T2	16		T10	3		T5	1429
valid_sources[0x0c]	24976	1			T2	142		T10	1		T5	1095
valid_sources[0x0d]	25122	1			T2	44		T3	4		T10	1
valid_sources[0x0e]	23773	1			T2	21		T5	1231		T30	2
valid_sources[0x0f]	24130	1			T2	2		T18	1		T23	1
valid_sources[0x10]	24572	1			T2	251		T3	14		T23	7
valid_sources[0x11]	27459	1			T2	187		T10	2		T47	21
valid_sources[0x12]	24132	1			T2	62		T23	3		T5	1365
valid_sources[0x13]	24763	1			T2	59		T5	1416		T30	3
valid_sources[0x14]	26065	1			T2	363		T75	2		T5	1197
valid_sources[0x15]	25602	1			T2	12		T23	2		T10	1
valid_sources[0x16]	25943	1			T2	8		T3	5		T23	6
valid_sources[0x17]	26218	1			T2	166		T5	1199		T11	1
valid_sources[0x18]	23825	1			T2	165		T3	1		T5	1209
valid_sources[0x19]	25453	1			T2	4		T3	3		T10	1
valid_sources[0x1a]	27289	1			T2	5		T5	1176		T77	1
valid_sources[0x1b]	25803	1			T2	164		T3	4		T23	4
valid_sources[0x1c]	23673	1			T2	7		T3	2		T18	2
valid_sources[0x1d]	23392	1			T2	226		T5	1217		T30	1
valid_sources[0x1e]	24677	1			T2	120		T5	1297		T77	3
valid_sources[0x1f]	26365	1			T2	139		T3	3		T10	1
valid_sources[0x20]	24597	1			T2	166		T5	1233		T30	3
valid_sources[0x21]	23109	1			T2	178		T3	2		T10	1
valid_sources[0x22]	25569	1			T2	28		T5	1267		T21	2
valid_sources[0x23]	26273	1			T2	100		T18	1		T10	2
valid_sources[0x24]	24711	1			T2	6		T23	7		T5	1291
valid_sources[0x25]	25292	1			T1	8		T2	278		T3	6
valid_sources[0x26]	24236	1			T2	15		T3	10		T76	2
valid_sources[0x27]	26363	1			T2	192		T10	2		T24	12
valid_sources[0x28]	25021	1			T2	143		T10	3		T26	12
valid_sources[0x29]	25893	1			T2	10		T3	2		T10	1
valid_sources[0x2a]	26328	1			T2	39		T3	2		T5	1404
valid_sources[0x2b]	24259	1			T2	157		T3	1		T5	1349
valid_sources[0x2c]	25645	1			T2	14		T18	2		T5	1347
valid_sources[0x2d]	23579	1			T2	23		T5	1333		T30	3
valid_sources[0x2e]	23732	1			T2	189		T3	1		T5	1434
valid_sources[0x2f]	25047	1			T1	10		T2	270		T23	5
valid_sources[0x30]	25418	1			T2	243		T3	6		T9	2
valid_sources[0x31]	23705	1			T2	65		T3	1		T18	1
valid_sources[0x32]	23935	1			T2	76		T4	1		T5	1390
valid_sources[0x33]	25791	1			T2	14		T9	1		T24	3
valid_sources[0x34]	23278	1			T2	36		T76	2		T5	1194
valid_sources[0x35]	25200	1			T2	168		T10	1		T5	1352
valid_sources[0x36]	23800	1			T2	150		T76	5		T5	1125
valid_sources[0x37]	24609	1			T2	120		T18	1		T76	2
valid_sources[0x38]	24759	1			T2	221		T5	1285		T48	3
valid_sources[0x39]	26313	1			T2	191		T3	1		T5	1263
valid_sources[0x3a]	27106	1			T2	355		T76	11		T5	1472
valid_sources[0x3b]	24435	1			T1	4		T2	12		T3	7
valid_sources[0x3c]	27274	1			T2	276		T3	2		T10	2
valid_sources[0x3d]	25163	1			T2	136		T18	1		T10	1
valid_sources[0x3e]	25237	1			T2	186		T3	6		T76	1
valid_sources[0x3f]	23933	1			T2	200		T3	2		T18	1
valid_sources[0x40]	23973	1			T2	65		T23	1		T75	1
valid_sources[0x41]	23999	1			T2	114		T23	2		T5	1503
valid_sources[0x42]	24836	1			T2	105		T5	1281		T48	1
valid_sources[0x43]	25274	1			T2	310		T5	1312		T77	2
valid_sources[0x44]	24219	1			T2	9		T24	1		T5	1361
valid_sources[0x45]	25274	1			T2	328		T3	9		T10	1
valid_sources[0x46]	23823	1			T2	15		T3	3		T76	1
valid_sources[0x47]	25266	1			T2	14		T23	3		T10	1
valid_sources[0x48]	26281	1			T2	8		T5	1171		T30	1
valid_sources[0x49]	26964	1			T2	6		T3	8		T10	1
valid_sources[0x4a]	24954	1			T2	9		T5	1255		T30	1
valid_sources[0x4b]	24217	1			T2	230		T3	4		T10	1
valid_sources[0x4c]	27746	1			T2	429		T23	1		T10	1
valid_sources[0x4d]	26296	1			T2	8		T3	15		T23	1
valid_sources[0x4e]	26416	1			T2	194		T5	1293		T11	2
valid_sources[0x4f]	26498	1			T1	2		T2	234		T3	1
valid_sources[0x50]	21774	1			T2	19		T76	1		T5	1260
valid_sources[0x51]	25039	1			T2	3		T3	1		T5	1248
valid_sources[0x52]	24901	1			T2	27		T3	4		T5	1228
valid_sources[0x53]	24996	1			T2	197		T3	6		T23	2
valid_sources[0x54]	26363	1			T1	4		T2	2		T3	4
valid_sources[0x55]	24277	1			T2	195		T10	1		T5	1394
valid_sources[0x56]	24824	1			T2	12		T5	1185		T21	1
valid_sources[0x57]	26559	1			T2	71		T9	2		T5	1344
valid_sources[0x58]	23363	1			T2	403		T10	1		T5	1236
valid_sources[0x59]	25680	1			T2	207		T5	1370		T30	3
valid_sources[0x5a]	24088	1			T2	19		T3	2		T18	2
valid_sources[0x5b]	24756	1			T2	84		T5	1294		T77	2
valid_sources[0x5c]	25662	1			T2	9		T10	3		T4	2
valid_sources[0x5d]	26502	1			T2	210		T3	3		T5	1231
valid_sources[0x5e]	27663	1			T2	36		T3	7		T18	2
valid_sources[0x5f]	26483	1			T1	2		T2	243		T3	3
valid_sources[0x60]	25507	1			T2	133		T5	1195		T77	1
valid_sources[0x61]	27898	1			T2	6		T3	6		T26	6
valid_sources[0x62]	25102	1			T2	19		T23	9		T76	1
valid_sources[0x63]	24332	1			T2	144		T3	1		T5	1363
valid_sources[0x64]	25723	1			T2	143		T18	1		T10	3
valid_sources[0x65]	22949	1			T2	19		T5	1058		T85	2
valid_sources[0x66]	23474	1			T2	33		T76	1		T5	1202
valid_sources[0x67]	28513	1			T2	154		T75	4		T5	1117
valid_sources[0x68]	26584	1			T2	164		T10	1		T5	1113
valid_sources[0x69]	26150	1			T2	124		T3	1		T18	1
valid_sources[0x6a]	26533	1			T2	31		T23	1		T10	1
valid_sources[0x6b]	25775	1			T2	427		T3	4		T23	3
valid_sources[0x6c]	27699	1			T2	12		T24	1		T5	1317
valid_sources[0x6d]	24287	1			T1	2		T2	17		T5	1366
valid_sources[0x6e]	24635	1			T2	17		T3	1		T23	5
valid_sources[0x6f]	26327	1			T2	126		T3	1		T5	1253
valid_sources[0x70]	23242	1			T2	95		T23	1		T24	5
valid_sources[0x71]	24996	1			T2	45		T18	2		T5	1233
valid_sources[0x72]	26649	1			T2	342		T3	2		T23	2
valid_sources[0x73]	23578	1			T1	15		T2	369		T3	3
valid_sources[0x74]	24433	1			T2	127		T5	1216		T21	1
valid_sources[0x75]	25810	1			T2	172		T18	1		T9	1
valid_sources[0x76]	27211	1			T2	2		T76	1		T5	1413
valid_sources[0x77]	24378	1			T2	154		T10	3		T5	1203
valid_sources[0x78]	24441	1			T1	3		T2	10		T5	1298
valid_sources[0x79]	25850	1			T2	21		T23	10		T5	1262
valid_sources[0x7a]	26708	1			T2	39		T3	2		T5	1301
valid_sources[0x7b]	24194	1			T2	5		T10	1		T5	1339
valid_sources[0x7c]	25349	1			T2	279		T3	1		T5	1381
valid_sources[0x7d]	25339	1			T2	128		T10	2		T75	1
valid_sources[0x7e]	24684	1			T2	21		T3	6		T10	1
valid_sources[0x7f]	24307	1			T2	367		T10	2		T76	4
valid_sources[0x80]	26249	1			T2	174		T3	1		T5	1375

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1438848

1

T1

3

T2

7987

T3

3

values[0x0]

all_enables

biggest_size

2135175

1

T1

18

T2

11871

T3

20

values[0x1]

all_enables

biggest_size

2130342

1

T1

19

T2

11634

T3

15