Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2821	1			T1	2		T2	12		T23	2
non_zero_bins[1]	1990	1			T1	3		T2	13		T3	3
zero	9468	1			T1	3		T2	47		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	574	1			T2	4		T3	1		T5	19
uni	3805	1			T1	1		T2	22		T3	1
gen	4492	1			T1	4		T2	20		T3	1
res	886	1			T1	2		T2	4		T23	1
ins	4522	1			T1	1		T2	22		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9242

1

T1

5

T2

52

T3

2

mubi_true

5037

1

T1

3

T2

20

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

13

1

T18

1

T266

1

T114

1

pass

14266

1

T1

8

T2

72

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	125	1			T5	6		T48	1		T59	1
upd	non_zero_bins[0]	pass	mubi_true	146	1			T5	2		T104	1		T38	4
upd	non_zero_bins[1]	pass	mubi_false	107	1			T2	3		T5	3		T86	1
upd	non_zero_bins[1]	pass	mubi_true	90	1			T2	1		T3	1		T5	6
upd	zero	pass	mubi_false	46	1			T5	1		T102	1		T38	1
upd	zero	pass	mubi_true	60	1			T5	1		T219	3		T221	2
uni	zero	pass	mubi_false	2817	1			T1	1		T2	16		T3	1
uni	zero	pass	mubi_true	988	1			T2	6		T5	32		T30	1
gen	non_zero_bins[0]	pass	mubi_false	460	1			T1	1		T2	3		T5	12
gen	non_zero_bins[0]	pass	mubi_true	525	1			T2	2		T23	1		T5	11
gen	non_zero_bins[1]	pass	mubi_false	392	1			T1	3		T2	3		T10	3
gen	non_zero_bins[1]	pass	mubi_true	422	1			T2	1		T3	1		T5	5
gen	zero	fail	mubi_false	11	1			T18	1		T266	1		T114	1
gen	zero	pass	mubi_false	1923	1			T2	10		T75	1		T4	1
gen	zero	pass	mubi_true	759	1			T2	1		T18	2		T9	2
res	non_zero_bins[0]	pass	mubi_false	194	1			T76	1		T5	4		T12	2
res	non_zero_bins[0]	pass	mubi_true	239	1			T23	1		T10	2		T5	4
res	non_zero_bins[1]	pass	mubi_false	105	1			T2	1		T5	2		T11	2
res	non_zero_bins[1]	pass	mubi_true	125	1			T5	2		T21	2		T39	2
res	zero	fail	mubi_false	2	1			T158	1		T159	1		-	-
res	zero	pass	mubi_false	107	1			T2	1		T5	1		T77	2
res	zero	pass	mubi_true	114	1			T1	2		T2	2		T5	2
ins	non_zero_bins[0]	pass	mubi_false	552	1			T2	4		T5	13		T48	1
ins	non_zero_bins[0]	pass	mubi_true	580	1			T1	1		T2	3		T5	25
ins	non_zero_bins[1]	pass	mubi_false	361	1			T2	1		T3	1		T5	11
ins	non_zero_bins[1]	pass	mubi_true	388	1			T2	3		T10	1		T5	11
ins	zero	pass	mubi_false	2040	1			T2	10		T18	1		T9	1
ins	zero	pass	mubi_true	601	1			T2	1		T18	1		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded