Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	649460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5027226

1

T1

22

T2

145

T3

45

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1514846	1			T1	27		T2	217		T3	152
values[0x0]	1921888	1			T1	9		T2	88		T3	25
values[0x1]	2239952	1			T1	13		T2	75		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	326655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5350031

1

T1

25

T2

201

T3

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22954	1			T3	1		T25	5		T5	5
valid_sources[0x01]	22363	1			T25	1		T5	5		T9	1
valid_sources[0x02]	22093	1			T3	2		T5	4		T16	1
valid_sources[0x03]	23094	1			T25	6		T5	3		T16	1
valid_sources[0x04]	23049	1			T25	4		T5	3		T19	1
valid_sources[0x05]	22532	1			T3	5		T25	3		T5	1
valid_sources[0x06]	23503	1			T2	14		T3	3		T25	5
valid_sources[0x07]	20160	1			T3	2		T5	2		T46	1
valid_sources[0x08]	23113	1			T3	3		T25	1		T5	2
valid_sources[0x09]	22488	1			T3	3		T25	2		T5	5
valid_sources[0x0a]	22031	1			T1	1		T25	1		T5	2
valid_sources[0x0b]	22506	1			T3	2		T25	5		T5	4
valid_sources[0x0c]	21557	1			T2	10		T3	1		T25	3
valid_sources[0x0d]	20440	1			T3	1		T5	8		T10	7
valid_sources[0x0e]	21786	1			T4	2		T25	3		T5	5
valid_sources[0x0f]	23096	1			T5	5		T9	2		T14	1
valid_sources[0x10]	21649	1			T3	2		T25	4		T19	1
valid_sources[0x11]	21678	1			T1	1		T2	11		T25	2
valid_sources[0x12]	22692	1			T25	2		T5	4		T27	42
valid_sources[0x13]	22711	1			T2	7		T3	1		T4	1
valid_sources[0x14]	23911	1			T25	7		T5	2		T9	11
valid_sources[0x15]	23245	1			T2	16		T5	7		T9	1
valid_sources[0x16]	22854	1			T5	6		T44	1		T54	1
valid_sources[0x17]	22609	1			T3	2		T25	1		T5	1
valid_sources[0x18]	22863	1			T2	1		T3	7		T5	4
valid_sources[0x19]	22301	1			T5	4		T19	1		T45	1
valid_sources[0x1a]	21061	1			T1	1		T5	5		T9	1
valid_sources[0x1b]	21283	1			T1	1		T5	2		T19	1
valid_sources[0x1c]	23062	1			T3	4		T25	2		T5	4
valid_sources[0x1d]	23342	1			T3	1		T5	6		T46	1
valid_sources[0x1e]	20350	1			T3	3		T25	1		T5	5
valid_sources[0x1f]	24231	1			T5	5		T10	1		T19	2
valid_sources[0x20]	24383	1			T3	1		T25	3		T5	3
valid_sources[0x21]	22223	1			T1	1		T25	3		T5	3
valid_sources[0x22]	23593	1			T3	4		T25	5		T5	1
valid_sources[0x23]	21329	1			T4	1		T5	3		T10	1
valid_sources[0x24]	23542	1			T1	1		T25	2		T5	3
valid_sources[0x25]	21894	1			T1	1		T25	2		T5	5
valid_sources[0x26]	24562	1			T5	6		T44	2		T54	5
valid_sources[0x27]	21500	1			T3	2		T5	2		T9	2
valid_sources[0x28]	20953	1			T3	2		T25	1		T5	5
valid_sources[0x29]	21018	1			T3	3		T5	1		T16	1
valid_sources[0x2a]	20292	1			T1	1		T5	5		T10	1
valid_sources[0x2b]	20507	1			T3	3		T5	5		T19	1
valid_sources[0x2c]	21719	1			T3	2		T5	9		T9	3
valid_sources[0x2d]	21364	1			T2	6		T25	5		T5	1
valid_sources[0x2e]	20774	1			T25	3		T5	2		T9	3
valid_sources[0x2f]	19932	1			T1	1		T25	2		T5	6
valid_sources[0x30]	22763	1			T3	1		T25	4		T19	1
valid_sources[0x31]	22614	1			T25	1		T5	8		T54	1
valid_sources[0x32]	22251	1			T5	2		T16	1		T45	1
valid_sources[0x33]	21204	1			T2	1		T25	1		T5	2
valid_sources[0x34]	21007	1			T2	2		T25	3		T5	1
valid_sources[0x35]	23828	1			T25	6		T5	7		T16	1
valid_sources[0x36]	21775	1			T25	4		T5	6		T19	2
valid_sources[0x37]	20892	1			T25	5		T5	5		T19	2
valid_sources[0x38]	22213	1			T3	1		T5	5		T19	1
valid_sources[0x39]	22081	1			T16	1		T10	2		T19	1
valid_sources[0x3a]	21620	1			T1	1		T25	5		T5	5
valid_sources[0x3b]	22490	1			T5	1		T45	1		T54	3
valid_sources[0x3c]	21288	1			T25	3		T5	2		T9	8
valid_sources[0x3d]	21492	1			T5	3		T54	5		T48	1
valid_sources[0x3e]	20119	1			T3	1		T5	3		T19	2
valid_sources[0x3f]	22186	1			T25	2		T5	5		T45	1
valid_sources[0x40]	22237	1			T1	2		T5	6		T19	1
valid_sources[0x41]	22474	1			T5	5		T46	3		T54	2
valid_sources[0x42]	20405	1			T2	13		T5	2		T16	6
valid_sources[0x43]	22463	1			T2	9		T5	1		T19	1
valid_sources[0x44]	22887	1			T25	6		T5	2		T16	7
valid_sources[0x45]	23009	1			T25	4		T5	2		T19	1
valid_sources[0x46]	21720	1			T5	7		T45	2		T14	1
valid_sources[0x47]	22973	1			T1	1		T3	2		T25	1
valid_sources[0x48]	20905	1			T5	6		T9	4		T19	2
valid_sources[0x49]	22468	1			T2	32		T3	1		T5	2
valid_sources[0x4a]	23911	1			T5	3		T44	1		T47	1
valid_sources[0x4b]	22750	1			T3	1		T5	4		T9	2
valid_sources[0x4c]	22584	1			T5	4		T44	1		T45	1
valid_sources[0x4d]	22689	1			T2	11		T4	1		T25	3
valid_sources[0x4e]	21659	1			T25	2		T5	4		T9	1
valid_sources[0x4f]	21842	1			T2	6		T25	4		T5	2
valid_sources[0x50]	20129	1			T1	1		T2	2		T5	5
valid_sources[0x51]	22321	1			T25	1		T73	24		T19	1
valid_sources[0x52]	23048	1			T3	1		T5	6		T46	1
valid_sources[0x53]	21820	1			T2	4		T5	6		T16	1
valid_sources[0x54]	21131	1			T25	4		T5	3		T29	1
valid_sources[0x55]	20344	1			T25	1		T5	6		T46	1
valid_sources[0x56]	24091	1			T2	18		T3	1		T5	3
valid_sources[0x57]	21308	1			T3	1		T25	7		T5	4
valid_sources[0x58]	22230	1			T25	9		T5	2		T54	2
valid_sources[0x59]	21612	1			T1	1		T2	1		T3	1
valid_sources[0x5a]	21986	1			T3	3		T25	2		T5	1
valid_sources[0x5b]	23368	1			T25	2		T5	3		T19	1
valid_sources[0x5c]	22353	1			T2	9		T4	1		T25	1
valid_sources[0x5d]	23344	1			T2	1		T5	4		T19	1
valid_sources[0x5e]	20626	1			T2	3		T3	1		T25	4
valid_sources[0x5f]	21541	1			T5	5		T9	10		T10	4
valid_sources[0x60]	22847	1			T25	8		T5	2		T45	1
valid_sources[0x61]	22661	1			T5	3		T10	3		T19	1
valid_sources[0x62]	23089	1			T25	1		T5	3		T46	1
valid_sources[0x63]	21057	1			T4	1		T5	1		T19	3
valid_sources[0x64]	22639	1			T25	5		T5	5		T46	2
valid_sources[0x65]	22243	1			T5	3		T9	7		T19	1
valid_sources[0x66]	23612	1			T5	1		T16	1		T45	1
valid_sources[0x67]	21883	1			T2	3		T3	5		T25	5
valid_sources[0x68]	21311	1			T5	3		T19	2		T54	2
valid_sources[0x69]	21661	1			T3	3		T5	3		T14	1
valid_sources[0x6a]	22689	1			T25	1		T5	2		T9	4
valid_sources[0x6b]	21098	1			T3	1		T5	5		T10	1
valid_sources[0x6c]	23729	1			T25	2		T5	6		T45	1
valid_sources[0x6d]	21773	1			T5	4		T19	1		T54	1
valid_sources[0x6e]	23713	1			T3	1		T5	2		T9	1
valid_sources[0x6f]	22763	1			T3	4		T25	1		T5	4
valid_sources[0x70]	22703	1			T3	2		T25	4		T5	5
valid_sources[0x71]	21108	1			T3	2		T25	6		T5	6
valid_sources[0x72]	20859	1			T2	4		T3	3		T5	1
valid_sources[0x73]	23011	1			T5	3		T10	1		T19	1
valid_sources[0x74]	22618	1			T25	3		T5	3		T29	1
valid_sources[0x75]	21340	1			T3	2		T5	6		T45	1
valid_sources[0x76]	22940	1			T3	1		T5	4		T9	7
valid_sources[0x77]	22853	1			T4	1		T25	6		T5	2
valid_sources[0x78]	22951	1			T3	3		T25	4		T5	4
valid_sources[0x79]	22403	1			T4	1		T5	6		T16	2
valid_sources[0x7a]	21379	1			T2	13		T3	2		T25	1
valid_sources[0x7b]	23533	1			T3	1		T5	2		T9	2
valid_sources[0x7c]	20876	1			T3	1		T25	3		T5	2
valid_sources[0x7d]	21827	1			T25	1		T5	3		T19	2
valid_sources[0x7e]	20268	1			T10	3		T19	1		T46	1
valid_sources[0x7f]	22071	1			T1	6		T3	2		T5	3
valid_sources[0x80]	23602	1			T25	4		T19	1		T46	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1267226

1

T1

11

T2

69

T3

6

values[0x0]

all_enables

biggest_size

1879769

1

T1

6

T2

47

T3

22

values[0x1]

all_enables

biggest_size

1880231

1

T1

5

T2

29

T3

17