Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2741	1			T2	3		T3	6		T5	9
non_zero_bins[1]	2012	1			T2	2		T25	2		T5	8
zero	9728	1			T1	5		T2	9		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	569	1			T2	1		T5	1		T26	2
uni	3840	1			T2	4		T3	1		T25	2
gen	4615	1			T1	3		T2	4		T3	4
res	886	1			T2	1		T3	2		T5	3
ins	4571	1			T1	2		T2	4		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9622

1

T1

2

T2

8

T3

4

mubi_true

4859

1

T1

3

T2

6

T3

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

20

1

T100

1

T278

1

T279

1

pass

14461

1

T1

5

T2

14

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	138	1			T26	1		T41	2		T280	1
upd	non_zero_bins[0]	pass	mubi_true	139	1			T2	1		T5	1		T41	1
upd	non_zero_bins[1]	pass	mubi_false	87	1			T41	1		T42	3		T43	3
upd	non_zero_bins[1]	pass	mubi_true	101	1			T26	1		T41	1		T42	2
upd	zero	pass	mubi_false	38	1			T43	1		T86	1		T281	1
upd	zero	pass	mubi_true	66	1			T28	1		T41	1		T43	1
uni	zero	pass	mubi_false	2838	1			T2	3		T3	1		T25	2
uni	zero	pass	mubi_true	1002	1			T2	1		T5	5		T26	4
gen	non_zero_bins[0]	pass	mubi_false	519	1			T3	3		T5	2		T26	1
gen	non_zero_bins[0]	pass	mubi_true	472	1			T2	1		T3	1		T5	1
gen	non_zero_bins[1]	pass	mubi_false	453	1			T5	2		T26	1		T28	1
gen	non_zero_bins[1]	pass	mubi_true	335	1			T2	1		T5	1		T26	2
gen	zero	fail	mubi_false	18	1			T100	1		T278	1		T279	1
gen	zero	pass	mubi_false	2023	1			T1	1		T2	2		T4	1
gen	zero	pass	mubi_true	795	1			T1	2		T26	2		T27	2
res	non_zero_bins[0]	pass	mubi_false	190	1			T20	1		T24	2		T69	1
res	non_zero_bins[0]	pass	mubi_true	220	1			T2	1		T3	2		T26	1
res	non_zero_bins[1]	pass	mubi_false	134	1			T56	1		T23	2		T42	1
res	non_zero_bins[1]	pass	mubi_true	152	1			T5	2		T26	1		T42	1
res	zero	fail	mubi_false	2	1			T141	1		T282	1		-	-
res	zero	pass	mubi_false	114	1			T5	1		T46	2		T44	1
res	zero	pass	mubi_true	74	1			T59	1		T41	2		T280	1
ins	non_zero_bins[0]	pass	mubi_false	525	1			T5	3		T26	1		T46	1
ins	non_zero_bins[0]	pass	mubi_true	538	1			T5	2		T26	3		T24	1
ins	non_zero_bins[1]	pass	mubi_false	403	1			T25	2		T5	1		T19	1
ins	non_zero_bins[1]	pass	mubi_true	347	1			T2	1		T5	2		T26	2
ins	zero	pass	mubi_false	2140	1			T1	1		T2	3		T4	1
ins	zero	pass	mubi_true	618	1			T1	1		T3	1		T4	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded