Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.33	100.00	94.44		94.59	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	94.44		94.59	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T90,T35
1	1	Covered	T1,T4,T27

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T47,T69
1	1	Covered	T3,T9,T16

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T27,T16
1	0	Covered	T4,T14,T35

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T27,T16
1	Covered	T4,T14,T35

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T27,T16
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T27
1	Covered	T4,T14,T35

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	70	94.59
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T9,T10
AutoCaptGenCnt	143	Covered	T3,T9,T10
AutoCaptReseedCnt	141	Covered	T3,T9,T10
AutoDispatch	125	Covered	T3,T9,T10
AutoFirstAckWait	119	Covered	T3,T9,T10
AutoLoadIns	69	Covered	T3,T9,T16
AutoSendGenCmd	150	Covered	T3,T9,T10
AutoSendReseedCmd	162	Covered	T3,T9,T19
BootDone	98	Covered	T1,T4,T28
BootGenAckWait	90	Covered	T1,T4,T27
BootInsAckWait	80	Covered	T1,T4,T27
BootLoadGen	85	Covered	T1,T4,T27
BootLoadIns	65	Covered	T1,T4,T27
BootLoadUni	102	Covered	T28,T10,T45
BootPulse	94	Covered	T1,T4,T27
BootUniAckWait	107	Covered	T28,T10,T45
Error	188	Covered	T4,T14,T35
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T27,T16
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T9,T10
AutoAckWait->Error	188	Not Covered
AutoAckWait->Idle	211	Covered	T20,T69,T84
AutoAckWait->RejectCsrngEntropy	188	Covered	T58,T75,T101
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T9,T10
AutoCaptGenCnt->Error	188	Covered	T6,T102
AutoCaptGenCnt->Idle	211	Covered	T20,T103,T104
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T105,T106,T107
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T9,T19
AutoCaptReseedCnt->Error	188	Covered	T108,T109,T110
AutoCaptReseedCnt->Idle	211	Covered	T111,T112,T113
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T10,T114,T115
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T9,T10
AutoDispatch->Error	188	Covered	T116
AutoDispatch->Idle	138	Covered	T3,T9,T19
AutoDispatch->RejectCsrngEntropy	188	Covered	T117,T118,T119
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T9,T10
AutoFirstAckWait->Error	188	Covered	T120,T121
AutoFirstAckWait->Idle	211	Covered	T84,T122,T123
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T124,T125,T126
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T9,T10
AutoLoadIns->Error	188	Covered	T8,T127,T128
AutoLoadIns->Idle	211	Covered	T16,T75,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T129,T93,T130
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T9,T10
AutoSendGenCmd->Error	188	Not Covered
AutoSendGenCmd->Idle	211	Covered	T131,T132,T133
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T134,T135,T136
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T9,T19
AutoSendReseedCmd->Error	188	Covered	T137,T98,T138
AutoSendReseedCmd->Idle	211	Covered	T69,T139,T140
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T141,T142,T97
BootDone->BootLoadUni	102	Covered	T28,T10,T45
BootDone->Error	188	Covered	T143,T144
BootDone->Idle	211	Covered	T90,T145,T146
BootDone->RejectCsrngEntropy	188	Covered	T1,T89,T76
BootGenAckWait->BootPulse	94	Covered	T1,T4,T27
BootGenAckWait->Error	188	Covered	T53,T147,T148
BootGenAckWait->Idle	211	Covered	T149,T150,T151
BootGenAckWait->RejectCsrngEntropy	188	Covered	T16,T47,T48
BootInsAckWait->BootLoadGen	85	Covered	T1,T4,T27
BootInsAckWait->Error	188	Covered	T152,T153,T154
BootInsAckWait->Idle	211	Covered	T4,T35,T72
BootInsAckWait->RejectCsrngEntropy	188	Covered	T63,T92,T155
BootLoadGen->BootGenAckWait	90	Covered	T1,T4,T27
BootLoadGen->Error	188	Covered	T156
BootLoadGen->Idle	211	Covered	T157,T158,T159
BootLoadGen->RejectCsrngEntropy	188	Covered	T160,T161,T162
BootLoadIns->BootInsAckWait	80	Covered	T1,T4,T27
BootLoadIns->Error	188	Covered	T4,T163,T164
BootLoadIns->Idle	211	Covered	T165,T166
BootLoadIns->RejectCsrngEntropy	188	Covered	T73,T167,T168
BootLoadUni->BootUniAckWait	107	Covered	T28,T10,T45
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T169,T170,T171
BootPulse->BootDone	98	Covered	T1,T4,T28
BootPulse->Error	188	Covered	T172,T173
BootPulse->Idle	211	Covered	T174,T175,T176
BootPulse->RejectCsrngEntropy	188	Covered	T27,T177,T178
BootUniAckWait->Error	188	Covered	T179
BootUniAckWait->Idle	112	Covered	T28,T10,T45
BootUniAckWait->RejectCsrngEntropy	188	Covered	T180,T181,T182
Idle->AutoLoadIns	69	Covered	T3,T9,T16
Idle->BootLoadIns	65	Covered	T1,T4,T27
Idle->Error	188	Covered	T15,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T1,T16,T10
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T183,T184,T185
RejectCsrngEntropy->Idle	211	Covered	T1,T27,T16
SWPortMode->Error	188	Covered	T14,T15,T17
SWPortMode->Idle	211	Covered	T1,T2,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T27,T73,T47

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T16
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T27
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T10,T45
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T10
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T10,T45
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T28,T45,T55
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T28,T10,T45
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T9,T16
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T9,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T9,T19
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T9,T19
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T27,T16
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T7,T15

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T14,T35
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T27,T16
0	-	-	1	Covered	T1,T4,T27
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	196539342	157702	0	0
FpvSecCmErrorStEscalate_A	196539342	158877	0	0
u_state_regs_A	196509024	196321139	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	157702	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	560	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1060	0	0
T67	0	560	0	0
T72	0	585	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	158877	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	561	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1061	0	0
T67	0	561	0	0
T72	0	586	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196509024	196321139	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	567	424	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0