Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T25
DataWait	75	Covered	T2,T3,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T174,T186,T187
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T25
DataWait->AckPls	80	Covered	T2,T3,T25
DataWait->Disabled	107	Covered	T188,T189,T158
DataWait->Error	99	Covered	T6,T7,T72
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T25
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T6,T7

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T25
Idle	-	1	0	-	Covered	T2,T3,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T25
DataWait	-	-	-	0	Covered	T2,T3,T25
AckPls	-	-	-	-	Covered	T2,T3,T25
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T4,T6,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1375775394	1117964	0	0
FpvSecCmErrorStEscalate_A	1375775394	1126189	0	0
u_state_regs_A	1375745076	1374429881	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1375775394	1117964	0	0
T4	5152	2603	0	0
T5	182042	0	0	0
T6	0	1812	0	0
T7	0	4270	0	0
T8	0	6762	0	0
T9	21259	0	0	0
T14	0	7749	0	0
T15	0	67571	0	0
T16	14518	0	0	0
T17	0	141155	0	0
T25	15554	0	0	0
T26	91147	0	0	0
T27	13118	0	0	0
T28	27174	0	0	0
T29	5782	0	0	0
T35	0	7770	0	0
T67	0	4270	0	0
T72	0	4445	0	0
T73	10703	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1375775394	1126189	0	0
T4	5152	2610	0	0
T5	182042	0	0	0
T6	0	1819	0	0
T7	0	4277	0	0
T8	0	6769	0	0
T9	21259	0	0	0
T14	0	7756	0	0
T15	0	68481	0	0
T16	14518	0	0	0
T17	0	142975	0	0
T25	15554	0	0	0
T26	91147	0	0	0
T27	13118	0	0	0
T28	27174	0	0	0
T29	5782	0	0	0
T35	0	7777	0	0
T67	0	4277	0	0
T72	0	4452	0	0
T73	10703	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1375745076	1374429881	0	0
T1	12803	12166	0	0
T2	73836	71974	0	0
T3	43967	43526	0	0
T4	4983	3982	0	0
T5	182042	176001	0	0
T9	21259	20713	0	0
T25	15554	15085	0	0
T26	91147	89236	0	0
T27	13118	12705	0	0
T28	27174	26698	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T9,T19
DataWait	75	Covered	T25,T9,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T9,T19
DataWait->AckPls	80	Covered	T25,T9,T19
DataWait->Disabled	107	Covered	T132
DataWait->Error	99	Covered	T6,T96,T192
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T9,T19
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T7,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T9,T19
Idle	-	1	0	-	Covered	T25,T9,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T9,T19
DataWait	-	-	-	0	Covered	T25,T9,T19
AckPls	-	-	-	-	Covered	T25,T9,T19
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	160052	0	0
FpvSecCmErrorStEscalate_A	196539342	161227	0	0
u_state_regs_A	196539342	196351457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	160052	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	161227	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T27,T9
DataWait	75	Covered	T25,T27,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T27,T9
DataWait->AckPls	80	Covered	T25,T27,T9
DataWait->Disabled	107	Covered	T158,T150
DataWait->Error	99	Covered	T72,T143,T120
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T27,T9
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T27,T9
Idle	-	1	0	-	Covered	T25,T27,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T27,T9
DataWait	-	-	-	0	Covered	T25,T27,T9
AckPls	-	-	-	-	Covered	T25,T27,T9
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	160052	0	0
FpvSecCmErrorStEscalate_A	196539342	161227	0	0
u_state_regs_A	196539342	196351457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	160052	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	161227	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T9,T28
DataWait	75	Covered	T25,T9,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T9,T28
DataWait->AckPls	80	Covered	T25,T9,T28
DataWait->Disabled	107	Covered	T193,T151,T194
DataWait->Error	99	Covered	T53,T195,T152
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T9,T28
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T9,T28
Idle	-	1	0	-	Covered	T25,T9,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T9,T28
DataWait	-	-	-	0	Covered	T25,T9,T28
AckPls	-	-	-	-	Covered	T25,T9,T28
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	160052	0	0
FpvSecCmErrorStEscalate_A	196539342	161227	0	0
u_state_regs_A	196539342	196351457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	160052	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	161227	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T27,T9
DataWait	75	Covered	T25,T27,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T27,T9
DataWait->AckPls	80	Covered	T25,T27,T9
DataWait->Disabled	107	Covered	T188,T103,T196
DataWait->Error	99	Covered	T197,T198,T199
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T27,T9
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T27,T9
Idle	-	1	0	-	Covered	T25,T27,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T27,T9
DataWait	-	-	-	0	Covered	T25,T9,T28
AckPls	-	-	-	-	Covered	T25,T27,T9
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	160052	0	0
FpvSecCmErrorStEscalate_A	196539342	161227	0	0
u_state_regs_A	196539342	196351457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	160052	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	161227	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T25
DataWait	75	Covered	T2,T3,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T174,T200
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T25
DataWait->AckPls	80	Covered	T2,T3,T25
DataWait->Disabled	107	Covered	T201,T133,T202
DataWait->Error	99	Covered	T7,T203,T204
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T35,T15,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T25
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T15,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T25
Idle	-	1	0	-	Covered	T2,T3,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T25
DataWait	-	-	-	0	Covered	T2,T3,T25
AckPls	-	-	-	-	Covered	T2,T3,T25
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T4,T6,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	157652	0	0
FpvSecCmErrorStEscalate_A	196539342	158827	0	0
u_state_regs_A	196509024	196321139	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	157652	0	0
T4	736	329	0	0
T5	26006	0	0	0
T6	0	216	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	158827	0	0
T4	736	330	0	0
T5	26006	0	0	0
T6	0	217	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196509024	196321139	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	567	424	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T9,T28
DataWait	75	Covered	T25,T9,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T186,T187
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T9,T28
DataWait->AckPls	80	Covered	T25,T9,T28
DataWait->Disabled	107	Covered	T189,T159,T205
DataWait->Error	99	Covered	T148
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T9,T28
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T9,T28
Idle	-	1	0	-	Covered	T25,T9,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T9,T28
DataWait	-	-	-	0	Covered	T25,T9,T28
AckPls	-	-	-	-	Covered	T25,T9,T28
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	160052	0	0
FpvSecCmErrorStEscalate_A	196539342	161227	0	0
u_state_regs_A	196539342	196351457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	160052	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	161227	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T25,T9
DataWait	75	Covered	T1,T25,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T14,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T206
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T25,T9
DataWait->AckPls	80	Covered	T1,T25,T9
DataWait->Disabled	107	Covered	T20,T157,T131
DataWait->Error	99	Covered	T8,T116,T207
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T17,T18
EndPointClear->Disabled	107	Covered	T190,T165,T191
EndPointClear->Error	99	Covered	T4,T35,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T25,T9
Idle->Disabled	107	Covered	T1,T2,T4
Idle->Error	99	Covered	T14,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T25,T9
Idle	-	1	0	-	Covered	T1,T25,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T25,T9
DataWait	-	-	-	0	Covered	T1,T25,T9
AckPls	-	-	-	-	Covered	T1,T25,T9
Error	-	-	-	-	Covered	T4,T14,T35
default	-	-	-	-	Covered	T15,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T14,T35
0	1	Covered	T1,T4,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196539342	160052	0	0
FpvSecCmErrorStEscalate_A	196539342	161227	0	0
u_state_regs_A	196539342	196351457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	160052	0	0
T4	736	379	0	0
T5	26006	0	0	0
T6	0	266	0	0
T7	0	610	0	0
T8	0	966	0	0
T9	3037	0	0	0
T14	0	1107	0	0
T15	0	9653	0	0
T16	2074	0	0	0
T17	0	20165	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1110	0	0
T67	0	610	0	0
T72	0	635	0	0
T73	1529	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	161227	0	0
T4	736	380	0	0
T5	26006	0	0	0
T6	0	267	0	0
T7	0	611	0	0
T8	0	967	0	0
T9	3037	0	0	0
T14	0	1108	0	0
T15	0	9783	0	0
T16	2074	0	0	0
T17	0	20425	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1111	0	0
T67	0	611	0	0
T72	0	636	0	0
T73	1529	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0