Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T32,T39
1	0	1	Covered	T3,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392331796	549151	0	0
DepthKnown_A	393078684	392702914	0	0
RvalidKnown_A	393078684	392702914	0	0
WreadyKnown_A	393078684	392702914	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392675064	620671	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392331796	549151	0	0
T3	12562	7817	0	0
T4	216	0	0	0
T5	52012	0	0	0
T9	6074	3279	0	0
T10	0	685	0	0
T16	4148	613	0	0
T19	0	3723	0	0
T20	0	3436	0	0
T24	0	4194	0	0
T25	4444	0	0	0
T26	26042	0	0	0
T27	3748	0	0	0
T28	7764	0	0	0
T29	1652	0	0	0
T46	0	1144	0	0
T47	0	206	0	0
T58	0	577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393078684	392702914	0	0
T1	3658	3476	0	0
T2	21096	20564	0	0
T3	12562	12436	0	0
T4	1472	1186	0	0
T5	52012	50286	0	0
T9	6074	5918	0	0
T25	4444	4310	0	0
T26	26042	25496	0	0
T27	3748	3630	0	0
T28	7764	7628	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393078684	392702914	0	0
T1	3658	3476	0	0
T2	21096	20564	0	0
T3	12562	12436	0	0
T4	1472	1186	0	0
T5	52012	50286	0	0
T9	6074	5918	0	0
T25	4444	4310	0	0
T26	26042	25496	0	0
T27	3748	3630	0	0
T28	7764	7628	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393078684	392702914	0	0
T1	3658	3476	0	0
T2	21096	20564	0	0
T3	12562	12436	0	0
T4	1472	1186	0	0
T5	52012	50286	0	0
T9	6074	5918	0	0
T25	4444	4310	0	0
T26	26042	25496	0	0
T27	3748	3630	0	0
T28	7764	7628	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392675064	620671	0	0
T3	12562	7817	0	0
T4	1472	261	0	0
T5	52012	0	0	0
T9	6074	3279	0	0
T10	0	685	0	0
T16	4148	613	0	0
T19	0	3723	0	0
T20	0	3436	0	0
T24	0	4194	0	0
T25	4444	0	0	0
T26	26042	0	0	0
T27	3748	0	0	0
T28	7764	0	0	0
T29	1652	0	0	0
T46	0	1144	0	0
T47	0	206	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T81,T82
1	0	1	Covered	T3,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	196165898	280259	0	0
DepthKnown_A	196539342	196351457	0	0
RvalidKnown_A	196539342	196351457	0	0
WreadyKnown_A	196539342	196351457	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	196337532	316097	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196165898	280259	0	0
T3	6281	3920	0	0
T4	108	0	0	0
T5	26006	0	0	0
T9	3037	1648	0	0
T10	0	341	0	0
T16	2074	355	0	0
T19	0	1869	0	0
T20	0	1785	0	0
T24	0	2132	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T46	0	615	0	0
T47	0	125	0	0
T58	0	282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	196337532	316097	0	0
T3	6281	3920	0	0
T4	736	129	0	0
T5	26006	0	0	0
T9	3037	1648	0	0
T10	0	341	0	0
T16	2074	355	0	0
T19	0	1869	0	0
T20	0	1785	0	0
T24	0	2132	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T46	0	615	0	0
T47	0	125	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T83,T84
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T39,T85
1	0	1	Covered	T3,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	196165898	268892	0	0
DepthKnown_A	196539342	196351457	0	0
RvalidKnown_A	196539342	196351457	0	0
WreadyKnown_A	196539342	196351457	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	196337532	304574	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196165898	268892	0	0
T3	6281	3897	0	0
T4	108	0	0	0
T5	26006	0	0	0
T9	3037	1631	0	0
T10	0	344	0	0
T16	2074	258	0	0
T19	0	1854	0	0
T20	0	1651	0	0
T24	0	2062	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T46	0	529	0	0
T47	0	81	0	0
T58	0	295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	196337532	304574	0	0
T3	6281	3897	0	0
T4	736	132	0	0
T5	26006	0	0	0
T9	3037	1631	0	0
T10	0	344	0	0
T16	2074	258	0	0
T19	0	1854	0	0
T20	0	1651	0	0
T24	0	2062	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T46	0	529	0	0
T47	0	81	0	0