Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	659608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5427100

1

T1

25

T2

30

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1600563	1			T1	29		T2	49		T3	34
values[0x0]	2074524	1			T1	12		T2	15		T3	30
values[0x1]	2411621	1			T1	12		T2	14		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	325800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5760908

1

T1

31

T2

42

T3

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22750	1			T32	1		T4	173		T6	291
valid_sources[0x01]	22313	1			T4	102		T6	292		T25	1
valid_sources[0x02]	23090	1			T2	2		T32	1		T4	125
valid_sources[0x03]	22604	1			T3	3		T16	4		T4	175
valid_sources[0x04]	23031	1			T4	27		T6	327		T11	2
valid_sources[0x05]	22063	1			T4	392		T6	253		T50	1
valid_sources[0x06]	24091	1			T4	212		T6	264		T17	1
valid_sources[0x07]	24442	1			T22	1		T16	2		T4	607
valid_sources[0x08]	24569	1			T23	1		T4	139		T6	277
valid_sources[0x09]	24190	1			T32	2		T16	1		T4	399
valid_sources[0x0a]	23248	1			T4	77		T6	281		T17	2
valid_sources[0x0b]	24192	1			T16	1		T4	24		T6	289
valid_sources[0x0c]	24402	1			T32	1		T4	14		T6	268
valid_sources[0x0d]	23745	1			T21	7		T32	4		T23	1
valid_sources[0x0e]	23868	1			T32	1		T4	358		T5	3
valid_sources[0x0f]	22948	1			T21	2		T4	342		T6	250
valid_sources[0x10]	24716	1			T4	408		T6	267		T11	2
valid_sources[0x11]	23500	1			T32	1		T4	111		T6	266
valid_sources[0x12]	25424	1			T2	2		T4	362		T6	228
valid_sources[0x13]	25053	1			T2	1		T16	2		T4	330
valid_sources[0x14]	23033	1			T4	333		T6	270		T50	1
valid_sources[0x15]	25089	1			T21	1		T4	145		T6	276
valid_sources[0x16]	24109	1			T4	41		T6	303		T11	1
valid_sources[0x17]	24166	1			T2	1		T32	2		T4	649
valid_sources[0x18]	23522	1			T32	2		T4	230		T6	312
valid_sources[0x19]	24068	1			T32	3		T4	257		T6	288
valid_sources[0x1a]	22047	1			T32	1		T4	110		T6	273
valid_sources[0x1b]	24859	1			T21	1		T16	3		T4	205
valid_sources[0x1c]	23688	1			T23	1		T4	193		T6	286
valid_sources[0x1d]	25144	1			T4	122		T6	272		T11	1
valid_sources[0x1e]	26053	1			T32	1		T4	26		T6	313
valid_sources[0x1f]	23584	1			T23	1		T4	19		T6	265
valid_sources[0x20]	23252	1			T23	2		T16	2		T4	503
valid_sources[0x21]	24186	1			T32	1		T4	84		T6	278
valid_sources[0x22]	24968	1			T23	1		T16	1		T4	339
valid_sources[0x23]	22518	1			T3	1		T4	393		T6	294
valid_sources[0x24]	22764	1			T16	3		T4	146		T6	222
valid_sources[0x25]	23279	1			T32	1		T4	209		T6	248
valid_sources[0x26]	23841	1			T32	1		T16	1		T4	20
valid_sources[0x27]	23211	1			T22	1		T4	58		T6	282
valid_sources[0x28]	24016	1			T4	295		T6	243		T17	1
valid_sources[0x29]	23936	1			T4	544		T6	279		T48	6
valid_sources[0x2a]	23004	1			T2	1		T4	156		T6	249
valid_sources[0x2b]	22762	1			T2	2		T23	1		T16	3
valid_sources[0x2c]	23775	1			T32	1		T16	5		T4	25
valid_sources[0x2d]	23549	1			T22	2		T4	24		T6	283
valid_sources[0x2e]	23145	1			T4	180		T6	282		T18	1
valid_sources[0x2f]	22472	1			T4	22		T6	273		T24	2
valid_sources[0x30]	22458	1			T32	2		T16	1		T4	422
valid_sources[0x31]	24245	1			T32	1		T23	1		T16	1
valid_sources[0x32]	23759	1			T1	2		T32	1		T4	126
valid_sources[0x33]	23263	1			T32	1		T4	44		T6	292
valid_sources[0x34]	23377	1			T23	1		T16	6		T4	211
valid_sources[0x35]	23683	1			T23	1		T16	1		T4	207
valid_sources[0x36]	24223	1			T32	1		T4	119		T6	272
valid_sources[0x37]	24797	1			T2	1		T4	74		T6	233
valid_sources[0x38]	24247	1			T4	330		T6	240		T11	1
valid_sources[0x39]	24218	1			T3	8		T32	1		T4	26
valid_sources[0x3a]	24306	1			T1	1		T3	2		T29	1
valid_sources[0x3b]	24281	1			T2	2		T3	2		T23	1
valid_sources[0x3c]	24873	1			T2	2		T4	18		T6	254
valid_sources[0x3d]	23760	1			T21	3		T23	2		T16	4
valid_sources[0x3e]	23015	1			T29	1		T4	82		T6	263
valid_sources[0x3f]	24425	1			T4	102		T6	259		T25	5
valid_sources[0x40]	24016	1			T16	2		T4	90		T6	251
valid_sources[0x41]	23517	1			T4	630		T6	255		T17	1
valid_sources[0x42]	25294	1			T4	224		T6	278		T25	6
valid_sources[0x43]	22230	1			T22	50		T16	1		T4	223
valid_sources[0x44]	23718	1			T16	4		T4	335		T6	250
valid_sources[0x45]	22810	1			T3	17		T4	100		T30	1
valid_sources[0x46]	23176	1			T4	433		T6	269		T24	69
valid_sources[0x47]	23292	1			T2	10		T21	1		T32	1
valid_sources[0x48]	23944	1			T4	468		T6	291		T11	1
valid_sources[0x49]	24245	1			T1	1		T32	1		T4	40
valid_sources[0x4a]	22993	1			T1	1		T16	2		T4	591
valid_sources[0x4b]	22237	1			T4	311		T6	247		T18	1
valid_sources[0x4c]	23236	1			T10	26		T16	3		T4	59
valid_sources[0x4d]	24277	1			T2	3		T16	2		T4	245
valid_sources[0x4e]	23453	1			T22	1		T4	153		T6	298
valid_sources[0x4f]	24876	1			T4	83		T6	268		T50	2
valid_sources[0x50]	23429	1			T3	4		T4	815		T6	252
valid_sources[0x51]	23674	1			T4	417		T6	250		T11	1
valid_sources[0x52]	24193	1			T4	390		T5	7		T6	312
valid_sources[0x53]	22111	1			T16	1		T4	355		T6	303
valid_sources[0x54]	23259	1			T1	1		T2	1		T4	325
valid_sources[0x55]	23262	1			T23	1		T4	161		T6	279
valid_sources[0x56]	24709	1			T23	1		T16	1		T4	341
valid_sources[0x57]	23591	1			T1	1		T4	52		T6	249
valid_sources[0x58]	24325	1			T16	1		T4	257		T6	282
valid_sources[0x59]	23278	1			T1	1		T4	184		T6	281
valid_sources[0x5a]	21970	1			T21	10		T4	12		T6	236
valid_sources[0x5b]	24422	1			T2	1		T16	1		T4	427
valid_sources[0x5c]	24938	1			T32	1		T16	3		T4	151
valid_sources[0x5d]	25470	1			T2	4		T21	1		T32	1
valid_sources[0x5e]	25044	1			T2	3		T23	2		T16	4
valid_sources[0x5f]	21716	1			T3	15		T32	1		T16	4
valid_sources[0x60]	24255	1			T4	15		T6	296		T49	1
valid_sources[0x61]	24130	1			T2	5		T3	1		T4	184
valid_sources[0x62]	24267	1			T2	2		T21	1		T23	2
valid_sources[0x63]	23641	1			T4	32		T6	274		T20	10
valid_sources[0x64]	25143	1			T1	1		T4	463		T6	278
valid_sources[0x65]	24245	1			T1	1		T4	348		T6	265
valid_sources[0x66]	22789	1			T32	1		T4	219		T6	306
valid_sources[0x67]	22648	1			T2	3		T4	441		T6	328
valid_sources[0x68]	23917	1			T1	1		T23	1		T4	384
valid_sources[0x69]	26352	1			T16	2		T4	41		T6	257
valid_sources[0x6a]	24095	1			T1	1		T32	2		T4	187
valid_sources[0x6b]	23395	1			T32	1		T4	46		T6	253
valid_sources[0x6c]	23296	1			T16	5		T4	177		T6	257
valid_sources[0x6d]	22837	1			T22	1		T4	170		T6	221
valid_sources[0x6e]	23667	1			T1	2		T4	173		T6	310
valid_sources[0x6f]	24395	1			T2	1		T16	1		T4	260
valid_sources[0x70]	23507	1			T4	64		T6	308		T49	1
valid_sources[0x71]	23713	1			T32	1		T4	54		T6	294
valid_sources[0x72]	24779	1			T1	1		T32	1		T4	278
valid_sources[0x73]	24217	1			T22	1		T32	3		T4	47
valid_sources[0x74]	24418	1			T32	1		T16	1		T4	19
valid_sources[0x75]	22450	1			T32	1		T4	32		T6	277
valid_sources[0x76]	24718	1			T1	1		T4	512		T6	346
valid_sources[0x77]	24219	1			T22	1		T4	117		T6	254
valid_sources[0x78]	23751	1			T23	1		T4	409		T6	264
valid_sources[0x79]	22670	1			T16	1		T4	466		T6	258
valid_sources[0x7a]	23912	1			T4	14		T6	301		T24	168
valid_sources[0x7b]	25073	1			T16	1		T4	146		T6	282
valid_sources[0x7c]	24572	1			T21	2		T4	313		T6	264
valid_sources[0x7d]	24716	1			T29	2		T4	196		T6	244
valid_sources[0x7e]	24020	1			T1	1		T4	434		T6	264
valid_sources[0x7f]	24675	1			T1	1		T3	2		T4	331
valid_sources[0x80]	25289	1			T32	1		T4	32		T6	280

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1366053

1

T1

12

T2

13

T3

11

values[0x0]

all_enables

biggest_size

2031316

1

T1

11

T2

10

T3

24

values[0x1]

all_enables

biggest_size

2029731

1

T1

2

T2

7

T3

21