Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2696	1			T10	5		T32	2		T16	7
non_zero_bins[1]	1929	1			T10	2		T32	1		T4	13
zero	9328	1			T1	8		T2	7		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	515	1			T32	1		T4	4		T6	4
uni	3721	1			T1	1		T21	1		T10	1
gen	4434	1			T1	4		T2	4		T3	3
res	834	1			T10	2		T16	2		T4	4
ins	4449	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9232

1

T1

3

T2

2

T3

2

mubi_true

4721

1

T1

5

T2

5

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

20

1

T3

1

T70

1

T141

1

pass

13933

1

T1

8

T2

7

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	124	1			T32	1		T4	1		T6	2
upd	non_zero_bins[0]	pass	mubi_true	132	1			T4	2		T50	1		T24	1
upd	non_zero_bins[1]	pass	mubi_false	80	1			T4	1		T91	1		T216	1
upd	non_zero_bins[1]	pass	mubi_true	83	1			T265	1		T266	1		T92	1
upd	zero	pass	mubi_false	52	1			T6	2		T24	2		T92	2
upd	zero	pass	mubi_true	44	1			T92	1		T93	1		T91	3
uni	zero	pass	mubi_false	2762	1			T1	1		T21	1		T10	1
uni	zero	pass	mubi_true	959	1			T23	1		T4	14		T6	16
gen	non_zero_bins[0]	pass	mubi_false	524	1			T16	4		T4	2		T6	1
gen	non_zero_bins[0]	pass	mubi_true	498	1			T10	4		T4	5		T6	4
gen	non_zero_bins[1]	pass	mubi_false	337	1			T32	1		T4	1		T6	3
gen	non_zero_bins[1]	pass	mubi_true	389	1			T4	1		T26	1		T24	3
gen	zero	fail	mubi_false	19	1			T3	1		T70	1		T141	1
gen	zero	pass	mubi_false	1975	1			T1	2		T2	1		T21	1
gen	zero	pass	mubi_true	692	1			T1	2		T2	3		T3	2
res	non_zero_bins[0]	pass	mubi_false	204	1			T4	2		T6	1		T18	2
res	non_zero_bins[0]	pass	mubi_true	178	1			T16	2		T6	1		T18	2
res	non_zero_bins[1]	pass	mubi_false	116	1			T6	1		T17	2		T28	1
res	non_zero_bins[1]	pass	mubi_true	159	1			T10	2		T51	1		T92	2
res	zero	fail	mubi_false	1	1			T267	1		-	-		-	-
res	zero	pass	mubi_false	93	1			T4	1		T24	1		T12	2
res	zero	pass	mubi_true	83	1			T4	1		T17	6		T11	2
ins	non_zero_bins[0]	pass	mubi_false	522	1			T10	1		T32	1		T4	4
ins	non_zero_bins[0]	pass	mubi_true	514	1			T16	1		T4	2		T6	6
ins	non_zero_bins[1]	pass	mubi_false	376	1			T4	5		T6	1		T17	1
ins	non_zero_bins[1]	pass	mubi_true	389	1			T4	5		T6	1		T25	1
ins	zero	pass	mubi_false	2047	1			T2	1		T3	1		T23	1
ins	zero	pass	mubi_true	601	1			T1	3		T2	2		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded