Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.33	100.00	94.44		94.59	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	94.44		94.59	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T20,T64
1	1	Covered	T1,T2,T21

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T17,T18
1	1	Covered	T2,T3,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T20,T55

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T20,T55

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T20,T55

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	70	94.59
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T3,T10
AutoCaptGenCnt	143	Covered	T2,T3,T10
AutoCaptReseedCnt	141	Covered	T2,T10,T16
AutoDispatch	125	Covered	T2,T3,T10
AutoFirstAckWait	119	Covered	T2,T3,T10
AutoLoadIns	69	Covered	T2,T3,T10
AutoSendGenCmd	150	Covered	T2,T3,T10
AutoSendReseedCmd	162	Covered	T10,T16,T17
BootDone	98	Covered	T1,T2,T21
BootGenAckWait	90	Covered	T1,T2,T21
BootInsAckWait	80	Covered	T1,T2,T21
BootLoadGen	85	Covered	T1,T2,T21
BootLoadIns	65	Covered	T1,T2,T21
BootLoadUni	102	Covered	T1,T2,T21
BootPulse	94	Covered	T1,T2,T21
BootUniAckWait	107	Covered	T1,T2,T21
Error	188	Covered	T14,T20,T55
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T2,T3
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T10,T16
AutoAckWait->Error	188	Covered	T140
AutoAckWait->Idle	211	Covered	T17,T18,T51
AutoAckWait->RejectCsrngEntropy	188	Covered	T3,T47,T141
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T3,T10
AutoCaptGenCnt->Error	188	Covered	T142,T143,T144
AutoCaptGenCnt->Idle	211	Covered	T68,T124,T120
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T73,T145,T146
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T16,T17
AutoCaptReseedCnt->Error	188	Covered	T147
AutoCaptReseedCnt->Idle	211	Covered	T148,T149,T150
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T2,T151,T152
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T3,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T10,T16
AutoDispatch->Error	188	Covered	T9,T153
AutoDispatch->Idle	138	Covered	T10,T16,T11
AutoDispatch->RejectCsrngEntropy	188	Covered	T154,T155,T156
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T3,T10
AutoFirstAckWait->Error	188	Not Covered
AutoFirstAckWait->Idle	211	Covered	T53,T74,T157
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T158,T159,T160
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T3,T10
AutoLoadIns->Error	188	Covered	T7,T41,T161
AutoLoadIns->Idle	211	Covered	T70,T97,T69
AutoLoadIns->RejectCsrngEntropy	188	Covered	T84,T162,T163
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T3,T10
AutoSendGenCmd->Error	188	Covered	T164
AutoSendGenCmd->Idle	211	Covered	T17,T18,T51
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T62,T96,T165
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T16,T17
AutoSendReseedCmd->Error	188	Covered	T166,T102,T167
AutoSendReseedCmd->Idle	211	Covered	T31,T168,T169
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T64,T100,T170
BootDone->BootLoadUni	102	Covered	T1,T2,T21
BootDone->Error	188	Covered	T137,T171,T172
BootDone->Idle	211	Covered	T173,T174,T117
BootDone->RejectCsrngEntropy	188	Covered	T1,T175,T176
BootGenAckWait->BootPulse	94	Covered	T1,T2,T21
BootGenAckWait->Error	188	Covered	T133
BootGenAckWait->Idle	211	Covered	T177,T129,T178
BootGenAckWait->RejectCsrngEntropy	188	Covered	T70,T69,T76
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T21
BootInsAckWait->Error	188	Covered	T20,T179,T119
BootInsAckWait->Idle	211	Covered	T111,T179,T135
BootInsAckWait->RejectCsrngEntropy	188	Covered	T21,T180,T104
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T21
BootLoadGen->Error	188	Covered	T181,T182
BootLoadGen->Idle	211	Covered	T20,T136,T113
BootLoadGen->RejectCsrngEntropy	188	Covered	T183,T184,T185
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T21
BootLoadIns->Error	188	Covered	T111,T186,T187
BootLoadIns->Idle	211	Covered	T109,T188,T189
BootLoadIns->RejectCsrngEntropy	188	Covered	T190,T191,T192
BootLoadUni->BootUniAckWait	107	Covered	T1,T2,T21
BootLoadUni->Error	188	Covered	T118,T193,T194
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T195,T196,T197
BootPulse->BootDone	98	Covered	T1,T2,T21
BootPulse->Error	188	Covered	T45
BootPulse->Idle	211	Covered	T198,T199,T106
BootPulse->RejectCsrngEntropy	188	Covered	T200,T201,T202
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T1,T2,T21
BootUniAckWait->RejectCsrngEntropy	188	Covered	T22,T48,T98
Idle->AutoLoadIns	69	Covered	T2,T3,T10
Idle->BootLoadIns	65	Covered	T1,T2,T21
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T2,T21,T48
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T58,T203,T204
RejectCsrngEntropy->Idle	211	Covered	T1,T2,T3
SWPortMode->Error	188	Covered	T14,T57,T60
SWPortMode->Idle	211	Covered	T3,T22,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T1,T3,T22

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T21
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T22,T48,T37
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T21
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T3,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T16,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T10,T16
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T3,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T16
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T16,T17
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T16,T17
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T20,T55
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T55,T61,T8

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T14,T20,T55
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	224894250	83958	0	0
FpvSecCmErrorStEscalate_A	224894250	84083	0	0
u_state_regs_A	224850737	224746001	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	83958	0	0
T7	0	302	0	0
T11	2787	0	0	0
T14	795	448	0	0
T18	1641	0	0	0
T20	2136	409	0	0
T25	4673	0	0	0
T26	1558	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T49	1751	0	0	0
T50	3489	0	0	0
T55	0	254	0	0
T57	0	705	0	0
T58	0	327	0	0
T60	0	1090	0	0
T61	0	1050	0	0
T111	0	449	0	0
T112	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	84083	0	0
T7	0	303	0	0
T11	2787	0	0	0
T14	795	449	0	0
T18	1641	0	0	0
T20	2136	410	0	0
T25	4673	0	0	0
T26	1558	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T49	1751	0	0	0
T50	3489	0	0	0
T55	0	255	0	0
T57	0	706	0	0
T58	0	328	0	0
T60	0	1091	0	0
T61	0	1051	0	0
T111	0	450	0	0
T112	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224850737	224746001	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0