Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T81,T82,T83
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T59,T80
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	449410286	1070941	0	0
DepthKnown_A	449788500	449579028	0	0
RvalidKnown_A	449788500	449579028	0	0
WreadyKnown_A	449788500	449579028	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	449788500	1170911	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449410286	1070941	0	0
T2	4686	670	0	0
T3	4316	474	0	0
T4	503010	0	0	0
T10	9362	7039	0	0
T11	0	2111	0	0
T16	3592	919	0	0
T17	0	5175	0	0
T18	0	2487	0	0
T21	3970	0	0	0
T22	5364	0	0	0
T23	3196	0	0	0
T29	2238	0	0	0
T31	0	2676	0	0
T32	7030	0	0	0
T47	0	436	0	0
T51	0	4165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449788500	449579028	0	0
T1	4460	4348	0	0
T2	4686	4532	0	0
T3	4316	4214	0	0
T10	9362	9204	0	0
T16	3592	3430	0	0
T21	3970	3808	0	0
T22	5364	5168	0	0
T23	3196	3010	0	0
T29	2238	2050	0	0
T32	7030	6888	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449788500	449579028	0	0
T1	4460	4348	0	0
T2	4686	4532	0	0
T3	4316	4214	0	0
T10	9362	9204	0	0
T16	3592	3430	0	0
T21	3970	3808	0	0
T22	5364	5168	0	0
T23	3196	3010	0	0
T29	2238	2050	0	0
T32	7030	6888	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449788500	449579028	0	0
T1	4460	4348	0	0
T2	4686	4532	0	0
T3	4316	4214	0	0
T10	9362	9204	0	0
T16	3592	3430	0	0
T21	3970	3808	0	0
T22	5364	5168	0	0
T23	3196	3010	0	0
T29	2238	2050	0	0
T32	7030	6888	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	449788500	1170911	0	0
T2	4686	670	0	0
T3	4316	474	0	0
T4	503010	0	0	0
T10	9362	7039	0	0
T11	0	2111	0	0
T14	0	283	0	0
T16	3592	919	0	0
T17	0	5175	0	0
T18	0	2487	0	0
T20	0	2285	0	0
T21	3970	0	0	0
T22	5364	0	0	0
T23	3196	0	0	0
T29	2238	0	0	0
T32	7030	0	0	0
T47	0	436	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T13,T84
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T85
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T59,T80
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	224705143	530255	0	0
DepthKnown_A	224894250	224789514	0	0
RvalidKnown_A	224894250	224789514	0	0
WreadyKnown_A	224894250	224789514	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	224894250	579715	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224705143	530255	0	0
T2	2343	337	0	0
T3	2158	230	0	0
T4	251505	0	0	0
T10	4681	3518	0	0
T11	0	986	0	0
T16	1796	449	0	0
T17	0	2518	0	0
T18	0	1193	0	0
T21	1985	0	0	0
T22	2682	0	0	0
T23	1598	0	0	0
T29	1119	0	0	0
T31	0	1322	0	0
T32	3515	0	0	0
T47	0	220	0	0
T51	0	2029	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	579715	0	0
T2	2343	337	0	0
T3	2158	230	0	0
T4	251505	0	0	0
T10	4681	3518	0	0
T11	0	986	0	0
T14	0	143	0	0
T16	1796	449	0	0
T17	0	2518	0	0
T18	0	1193	0	0
T20	0	1146	0	0
T21	1985	0	0	0
T22	2682	0	0	0
T23	1598	0	0	0
T29	1119	0	0	0
T32	3515	0	0	0
T47	0	220	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T81,T82,T83
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T86,T87
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	224705143	540686	0	0
DepthKnown_A	224894250	224789514	0	0
RvalidKnown_A	224894250	224789514	0	0
WreadyKnown_A	224894250	224789514	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	224894250	591196	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224705143	540686	0	0
T2	2343	333	0	0
T3	2158	244	0	0
T4	251505	0	0	0
T10	4681	3521	0	0
T11	0	1125	0	0
T16	1796	470	0	0
T17	0	2657	0	0
T18	0	1294	0	0
T21	1985	0	0	0
T22	2682	0	0	0
T23	1598	0	0	0
T29	1119	0	0	0
T31	0	1354	0	0
T32	3515	0	0	0
T47	0	216	0	0
T51	0	2136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	591196	0	0
T2	2343	333	0	0
T3	2158	244	0	0
T4	251505	0	0	0
T10	4681	3521	0	0
T11	0	1125	0	0
T14	0	140	0	0
T16	1796	470	0	0
T17	0	2657	0	0
T18	0	1294	0	0
T20	0	1139	0	0
T21	1985	0	0	0
T22	2682	0	0	0
T23	1598	0	0	0
T29	1119	0	0	0
T32	3515	0	0	0
T47	0	216	0	0