Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2758	1			T19	2		T24	1		T18	3
non_zero_bins[1]	1862	1			T19	1		T21	21		T41	4
zero	9405	1			T1	6		T2	5		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	521	1			T19	1		T21	6		T52	2
uni	3702	1			T19	1		T24	2		T18	3
gen	4469	1			T1	3		T2	2		T3	2
res	894	1			T1	1		T24	1		T18	1
ins	4439	1			T1	2		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9283

1

T1

3

T2

3

T3

1

mubi_true

4742

1

T1

3

T2

2

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

21

1

T280

1

T190

1

T287

1

pass

14004

1

T1

6

T2

5

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	118	1			T52	1		T288	1		T289	1
upd	non_zero_bins[0]	pass	mubi_true	126	1			T19	1		T22	2		T133	2
upd	non_zero_bins[1]	pass	mubi_false	74	1			T227	1		T133	3		T290	1
upd	non_zero_bins[1]	pass	mubi_true	101	1			T21	2		T22	2		T138	1
upd	zero	pass	mubi_false	46	1			T21	1		T22	1		T64	1
upd	zero	pass	mubi_true	56	1			T21	3		T52	1		T36	1
uni	zero	pass	mubi_false	2785	1			T19	1		T24	2		T18	1
uni	zero	pass	mubi_true	917	1			T18	2		T21	9		T25	1
gen	non_zero_bins[0]	pass	mubi_false	504	1			T18	1		T12	1		T21	1
gen	non_zero_bins[0]	pass	mubi_true	554	1			T19	1		T24	1		T21	6
gen	non_zero_bins[1]	pass	mubi_false	327	1			T21	3		T41	2		T17	1
gen	non_zero_bins[1]	pass	mubi_true	349	1			T21	4		T17	3		T52	1
gen	zero	fail	mubi_false	20	1			T280	1		T190	1		T287	1
gen	zero	pass	mubi_false	1984	1			T1	1		T18	2		T8	1
gen	zero	pass	mubi_true	731	1			T1	2		T2	2		T3	2
res	non_zero_bins[0]	pass	mubi_false	196	1			T21	1		T41	1		T26	1
res	non_zero_bins[0]	pass	mubi_true	203	1			T18	1		T12	2		T21	1
res	non_zero_bins[1]	pass	mubi_false	131	1			T52	1		T55	1		T22	1
res	non_zero_bins[1]	pass	mubi_true	161	1			T21	1		T14	2		T15	1
res	zero	fail	mubi_false	1	1			T180	1		-	-		-	-
res	zero	pass	mubi_false	101	1			T1	1		T21	1		T40	1
res	zero	pass	mubi_true	101	1			T24	1		T21	1		T41	1
ins	non_zero_bins[0]	pass	mubi_false	541	1			T18	1		T21	6		T14	1
ins	non_zero_bins[0]	pass	mubi_true	516	1			T21	3		T25	1		T41	1
ins	non_zero_bins[1]	pass	mubi_false	371	1			T19	1		T21	7		T41	1
ins	non_zero_bins[1]	pass	mubi_true	348	1			T21	4		T41	1		T52	1
ins	zero	pass	mubi_false	2084	1			T1	1		T2	3		T3	1
ins	zero	pass	mubi_true	579	1			T1	1		T3	1		T24	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded