Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T2,T33,T5
1	1	Covered	T2,T3,T24

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T19
1	0	Covered	T4,T8,T15
1	1	Covered	T1,T3,T4

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T2,T4,T5

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T2,T4,T5

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T8,T12
AutoCaptGenCnt	143	Covered	T1,T8,T12
AutoCaptReseedCnt	141	Covered	T1,T12,T14
AutoDispatch	125	Covered	T1,T8,T12
AutoFirstAckWait	119	Covered	T1,T8,T12
AutoLoadIns	69	Covered	T1,T3,T4
AutoSendGenCmd	150	Covered	T1,T8,T12
AutoSendReseedCmd	162	Covered	T1,T12,T14
BootDone	98	Covered	T2,T24,T33
BootGenAckWait	90	Covered	T2,T24,T33
BootInsAckWait	80	Covered	T2,T3,T24
BootLoadGen	85	Covered	T2,T3,T24
BootLoadIns	65	Covered	T2,T3,T24
BootLoadUni	102	Covered	T2,T24,T31
BootPulse	94	Covered	T2,T24,T33
BootUniAckWait	107	Covered	T24,T31,T27
Error	188	Covered	T2,T4,T5
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T3,T8
SWPortMode	74	Covered	T1,T3,T19

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T12,T14
AutoAckWait->Error	188	Covered	T145,T146
AutoAckWait->Idle	211	Covered	T15,T55,T68
AutoAckWait->RejectCsrngEntropy	188	Covered	T1,T8,T39
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T8,T12
AutoCaptGenCnt->Error	188	Covered	T147,T148,T149
AutoCaptGenCnt->Idle	211	Covered	T15,T124,T113
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T150,T151,T152
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T12,T14
AutoCaptReseedCnt->Error	188	Covered	T153,T154
AutoCaptReseedCnt->Idle	211	Covered	T85,T155,T156
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T157,T158,T159
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T8,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T12,T14
AutoDispatch->Error	188	Not Covered
AutoDispatch->Idle	138	Covered	T12,T14,T17
AutoDispatch->RejectCsrngEntropy	188	Covered	T160,T161,T162
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T8,T12
AutoFirstAckWait->Error	188	Covered	T163
AutoFirstAckWait->Idle	211	Covered	T164,T165,T166
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T72,T167,T168
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T8,T12
AutoLoadIns->Error	188	Covered	T4,T6,T44
AutoLoadIns->Idle	211	Covered	T3,T4,T27
AutoLoadIns->RejectCsrngEntropy	188	Covered	T139,T169,T170
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T8,T12
AutoSendGenCmd->Error	188	Covered	T116,T171,T172
AutoSendGenCmd->Idle	211	Covered	T93,T107,T119
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T173,T174,T175
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T12,T14
AutoSendReseedCmd->Error	188	Covered	T7,T47,T176
AutoSendReseedCmd->Idle	211	Covered	T177,T178,T179
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T141,T180,T181
BootDone->BootLoadUni	102	Covered	T2,T24,T31
BootDone->Error	188	Covered	T13,T182,T183
BootDone->Idle	211	Covered	T184,T185,T186
BootDone->RejectCsrngEntropy	188	Covered	T187,T188,T189
BootGenAckWait->BootPulse	94	Covered	T2,T24,T33
BootGenAckWait->Error	188	Covered	T46
BootGenAckWait->Idle	211	Covered	T33,T5,T42
BootGenAckWait->RejectCsrngEntropy	188	Covered	T134,T142,T190
BootInsAckWait->BootLoadGen	85	Covered	T2,T3,T24
BootInsAckWait->Error	188	Covered	T191,T192,T193
BootInsAckWait->Idle	211	Covered	T2,T49,T13
BootInsAckWait->RejectCsrngEntropy	188	Covered	T57,T194,T195
BootLoadGen->BootGenAckWait	90	Covered	T2,T24,T33
BootLoadGen->Error	188	Covered	T196,T197
BootLoadGen->Idle	211	Covered	T125,T112,T114
BootLoadGen->RejectCsrngEntropy	188	Covered	T3,T140,T198
BootLoadIns->BootInsAckWait	80	Covered	T2,T3,T24
BootLoadIns->Error	188	Covered	T42,T43,T97
BootLoadIns->Idle	211	Covered	T199,T200,T201
BootLoadIns->RejectCsrngEntropy	188	Covered	T202,T203,T204
BootLoadUni->BootUniAckWait	107	Covered	T24,T31,T27
BootLoadUni->Error	188	Covered	T2,T49
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T205,T206,T207
BootPulse->BootDone	98	Covered	T2,T24,T33
BootPulse->Error	188	Covered	T48,T208
BootPulse->Idle	211	Covered	T32,T91,T92
BootPulse->RejectCsrngEntropy	188	Covered	T209,T210,T211
BootUniAckWait->Error	188	Covered	T212,T213,T121
BootUniAckWait->Idle	112	Covered	T24,T31,T29
BootUniAckWait->RejectCsrngEntropy	188	Covered	T31,T27,T29
Idle->AutoLoadIns	69	Covered	T1,T3,T4
Idle->BootLoadIns	65	Covered	T2,T3,T24
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T1,T27,T29
Idle->SWPortMode	74	Covered	T1,T3,T19
RejectCsrngEntropy->Error	188	Covered	T59,T214,T215
RejectCsrngEntropy->Idle	211	Covered	T1,T3,T8
SWPortMode->Error	188	Covered	T58,T60,T45
SWPortMode->Idle	211	Covered	T1,T8,T21
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T8,T31

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T24
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T33
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T33
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T33
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T24,T31
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T33,T5
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T31
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T31,T27
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T24,T31,T27
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T8,T12
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T3,T4
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T8,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T8,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T8,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T8,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T12,T14,T17
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T12,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T8,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T8,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T12,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T12,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T14,T17
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T105,T63

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T3,T8
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	216344672	84861	0	0
FpvSecCmErrorStEscalate_A	216344672	84984	0	0
u_state_regs_A	216302647	216195541	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	84861	0	0
T2	2046	1181	0	0
T3	2503	0	0	0
T4	2930	854	0	0
T5	0	352	0	0
T6	0	201	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	397	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	297	0	0
T49	0	393	0	0
T58	0	626	0	0
T59	0	634	0	0
T60	0	230	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	84984	0	0
T2	2046	1182	0	0
T3	2503	0	0	0
T4	2930	855	0	0
T5	0	353	0	0
T6	0	202	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	398	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	298	0	0
T49	0	394	0	0
T58	0	627	0	0
T59	0	635	0	0
T60	0	231	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216302647	216195541	0	0
T1	2576	2485	0	0
T2	1776	1609	0	0
T3	2503	2429	0	0
T4	1710	1549	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0