Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.46 100.00 100.00 78.57 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.60 100.00 100.00 78.57 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 100.00 100.00 85.71 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 100.00 100.00 85.71 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 100.00 100.00 85.71 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 100.00 100.00 85.71 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 100.00 100.00 85.71 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 100.00 100.00 85.71 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 100.00 100.00 85.71 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 100.00 100.00 85.71 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 100.00 100.00 85.71 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 100.00 100.00 85.71 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T3,T19
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T32,T91,T92
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T3,T19
DataWait->AckPls 80 Covered T1,T3,T19
DataWait->Disabled 107 Covered T15,T62,T93
DataWait->Error 99 Covered T2,T4,T5
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T2,T4,T5



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T3,T19
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T3,T19
DataWait - - - 0 Covered T1,T2,T3
AckPls - - - - Covered T1,T3,T19
Error - - - - Covered T2,T4,T5
default - - - - Covered T2,T49,T58


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 1514412704 608477 0 0
FpvSecCmErrorStEscalate_A 1514412704 609338 0 0
u_state_regs_A 1514370679 1513620937 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1514412704 608477 0 0
T2 14322 8217 0 0
T3 17521 0 0 0
T4 20510 5978 0 0
T5 0 2814 0 0
T6 0 1407 0 0
T8 12432 0 0 0
T12 44786 0 0 0
T13 0 2779 0 0
T18 43183 0 0 0
T19 24192 0 0 0
T20 9142 0 0 0
T24 10472 0 0 0
T33 7294 0 0 0
T42 0 2079 0 0
T49 0 2701 0 0
T58 0 4332 0 0
T59 0 4388 0 0
T60 0 1560 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1514412704 609338 0 0
T2 14322 8224 0 0
T3 17521 0 0 0
T4 20510 5985 0 0
T5 0 2821 0 0
T6 0 1414 0 0
T8 12432 0 0 0
T12 44786 0 0 0
T13 0 2786 0 0
T18 43183 0 0 0
T19 24192 0 0 0
T20 9142 0 0 0
T24 10472 0 0 0
T33 7294 0 0 0
T42 0 2086 0 0
T49 0 2708 0 0
T58 0 4339 0 0
T59 0 4395 0 0
T60 0 1567 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1514370679 1513620937 0 0
T1 18032 17395 0 0
T2 14052 12883 0 0
T3 17521 17003 0 0
T4 19290 18163 0 0
T8 12432 12026 0 0
T18 43183 42490 0 0
T19 24192 23583 0 0
T20 9142 8505 0 0
T24 10472 9919 0 0
T33 7294 6720 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 11 78.57
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T3,T8
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T3,T8
DataWait->AckPls 80 Covered T1,T3,T8
DataWait->Disabled 107 Covered T98,T99,T100
DataWait->Error 99 Covered T2,T101,T102
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T4,T5,T49



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 15 93.75
IF 52 2 2 100.00
CASE 60 11 10 90.91
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T3,T8
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T3,T8
DataWait - - - 0 Covered T2,T3,T8
AckPls - - - - Covered T1,T3,T8
Error - - - - Covered T2,T4,T5
default - - - - Not Covered


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 87161 0 0
FpvSecCmErrorStEscalate_A 216344672 87284 0 0
u_state_regs_A 216344672 216237566 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87161 0 0
T2 2046 1181 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 393 0 0
T58 0 626 0 0
T59 0 634 0 0
T60 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87284 0 0
T2 2046 1182 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 394 0 0
T58 0 627 0 0
T59 0 635 0 0
T60 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 216237566 0 0
T1 2576 2485 0 0
T2 2046 1879 0 0
T3 2503 2429 0 0
T4 2930 2769 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T25,T26,T30
DataWait 75 Covered T25,T26,T13
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T103
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T25,T26,T30
DataWait->AckPls 80 Covered T25,T26,T30
DataWait->Disabled 107 Covered T62,T93,T104
DataWait->Error 99 Covered T13,T6,T105
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T25,T26,T13
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T2,T4,T5



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 15 93.75
IF 52 2 2 100.00
CASE 60 11 10 90.91
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T25,T26,T30
Idle - 1 0 - Covered T25,T26,T13
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T25,T26,T30
DataWait - - - 0 Covered T25,T26,T13
AckPls - - - - Covered T25,T26,T30
Error - - - - Covered T2,T4,T5
default - - - - Not Covered


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 87161 0 0
FpvSecCmErrorStEscalate_A 216344672 87284 0 0
u_state_regs_A 216344672 216237566 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87161 0 0
T2 2046 1181 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 393 0 0
T58 0 626 0 0
T59 0 634 0 0
T60 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87284 0 0
T2 2046 1182 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 394 0 0
T58 0 627 0 0
T59 0 635 0 0
T60 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 216237566 0 0
T1 2576 2485 0 0
T2 2046 1879 0 0
T3 2503 2429 0 0
T4 2930 2769 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T25,T26,T15
DataWait 75 Covered T25,T26,T15
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T106
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T25,T26,T15
DataWait->AckPls 80 Covered T25,T26,T15
DataWait->Disabled 107 Covered T15,T107,T108
DataWait->Error 99 Covered T109,T110,T111
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T25,T26,T15
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T2,T4,T5



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 15 93.75
IF 52 2 2 100.00
CASE 60 11 10 90.91
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T25,T26,T15
Idle - 1 0 - Covered T25,T26,T15
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T25,T26,T15
DataWait - - - 0 Covered T25,T26,T15
AckPls - - - - Covered T25,T26,T15
Error - - - - Covered T2,T4,T5
default - - - - Not Covered


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 87161 0 0
FpvSecCmErrorStEscalate_A 216344672 87284 0 0
u_state_regs_A 216344672 216237566 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87161 0 0
T2 2046 1181 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 393 0 0
T58 0 626 0 0
T59 0 634 0 0
T60 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87284 0 0
T2 2046 1182 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 394 0 0
T58 0 627 0 0
T59 0 635 0 0
T60 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 216237566 0 0
T1 2576 2485 0 0
T2 2046 1879 0 0
T3 2503 2429 0 0
T4 2930 2769 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T25,T27,T28
DataWait 75 Covered T25,T27,T28
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T92
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T25,T27,T28
DataWait->AckPls 80 Covered T25,T27,T28
DataWait->Disabled 107 Covered T112,T113,T114
DataWait->Error 99 Covered T115,T116
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T25,T27,T28
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T2,T4,T5



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 15 93.75
IF 52 2 2 100.00
CASE 60 11 10 90.91
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T25,T27,T28
Idle - 1 0 - Covered T25,T27,T28
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T25,T27,T28
DataWait - - - 0 Covered T25,T28,T40
AckPls - - - - Covered T25,T27,T28
Error - - - - Covered T2,T4,T5
default - - - - Not Covered


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 87161 0 0
FpvSecCmErrorStEscalate_A 216344672 87284 0 0
u_state_regs_A 216344672 216237566 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87161 0 0
T2 2046 1181 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 393 0 0
T58 0 626 0 0
T59 0 634 0 0
T60 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87284 0 0
T2 2046 1182 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 394 0 0
T58 0 627 0 0
T59 0 635 0 0
T60 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 216237566 0 0
T1 2576 2485 0 0
T2 2046 1879 0 0
T3 2503 2429 0 0
T4 2930 2769 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T25,T29,T30
DataWait 75 Covered T25,T29,T30
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T117
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T25,T29,T30
DataWait->AckPls 80 Covered T25,T29,T30
DataWait->Disabled 107 Covered T118,T119
DataWait->Error 99 Covered T120,T121,T122
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T25,T29,T30
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T2,T4,T5



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 15 93.75
IF 52 2 2 100.00
CASE 60 11 10 90.91
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T25,T29,T30
Idle - 1 0 - Covered T25,T29,T30
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T25,T29,T30
DataWait - - - 0 Covered T25,T29,T30
AckPls - - - - Covered T25,T29,T30
Error - - - - Covered T2,T4,T5
default - - - - Not Covered


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 87161 0 0
FpvSecCmErrorStEscalate_A 216344672 87284 0 0
u_state_regs_A 216344672 216237566 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87161 0 0
T2 2046 1181 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 393 0 0
T58 0 626 0 0
T59 0 634 0 0
T60 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87284 0 0
T2 2046 1182 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 394 0 0
T58 0 627 0 0
T59 0 635 0 0
T60 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 216237566 0 0
T1 2576 2485 0 0
T2 2046 1879 0 0
T3 2503 2429 0 0
T4 2930 2769 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T31,T32,T25
DataWait 75 Covered T31,T32,T25
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T32,T123
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T31,T32,T25
DataWait->AckPls 80 Covered T31,T32,T25
DataWait->Disabled 107 Covered T124,T125,T126
DataWait->Error 99 Covered T127
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T31,T32,T25
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T2,T4,T5



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 15 93.75
IF 52 2 2 100.00
CASE 60 11 10 90.91
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T31,T32,T25
Idle - 1 0 - Covered T31,T32,T25
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T31,T32,T25
DataWait - - - 0 Covered T31,T32,T25
AckPls - - - - Covered T31,T32,T25
Error - - - - Covered T2,T4,T5
default - - - - Not Covered


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 87161 0 0
FpvSecCmErrorStEscalate_A 216344672 87284 0 0
u_state_regs_A 216344672 216237566 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87161 0 0
T2 2046 1181 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 393 0 0
T58 0 626 0 0
T59 0 634 0 0
T60 0 230 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 87284 0 0
T2 2046 1182 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 394 0 0
T58 0 627 0 0
T59 0 635 0 0
T60 0 231 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 216237566 0 0
T1 2576 2485 0 0
T2 2046 1879 0 0
T3 2503 2429 0 0
T4 2930 2769 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T19,T24
DataWait 75 Covered T1,T19,T24
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T2,T4,T5
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T91
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T19,T24
DataWait->AckPls 80 Covered T1,T19,T24
DataWait->Disabled 107 Covered T128,T129
DataWait->Error 99 Covered T4,T5,T44
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Not Covered
EndPointClear->Disabled 107 Covered T94,T95,T96
EndPointClear->Error 99 Covered T42,T43,T97
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T19,T24
Idle->Disabled 107 Covered T1,T2,T3
Idle->Error 99 Covered T13,T6,T105



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T19,T24
Idle - 1 0 - Covered T1,T19,T24
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T19,T24
DataWait - - - 0 Covered T1,T19,T24
AckPls - - - - Covered T1,T19,T24
Error - - - - Covered T2,T4,T5
default - - - - Covered T2,T49,T58


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T2,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 216344672 85511 0 0
FpvSecCmErrorStEscalate_A 216344672 85634 0 0
u_state_regs_A 216302647 216195541 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 85511 0 0
T2 2046 1131 0 0
T3 2503 0 0 0
T4 2930 854 0 0
T5 0 402 0 0
T6 0 201 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 397 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 297 0 0
T49 0 343 0 0
T58 0 576 0 0
T59 0 584 0 0
T60 0 180 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216344672 85634 0 0
T2 2046 1132 0 0
T3 2503 0 0 0
T4 2930 855 0 0
T5 0 403 0 0
T6 0 202 0 0
T8 1776 0 0 0
T12 6398 0 0 0
T13 0 398 0 0
T18 6169 0 0 0
T19 3456 0 0 0
T20 1306 0 0 0
T24 1496 0 0 0
T33 1042 0 0 0
T42 0 298 0 0
T49 0 344 0 0
T58 0 577 0 0
T59 0 585 0 0
T60 0 181 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216302647 216195541 0 0
T1 2576 2485 0 0
T2 1776 1609 0 0
T3 2503 2429 0 0
T4 1710 1549 0 0
T8 1776 1718 0 0
T18 6169 6070 0 0
T19 3456 3369 0 0
T20 1306 1215 0 0
T24 1496 1417 0 0
T33 1042 960 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%