Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T80,T82,T83
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T79,T81,T77
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	432300522	1868863	0	0
DepthKnown_A	432689344	432475132	0	0
RvalidKnown_A	432689344	432475132	0	0
WreadyKnown_A	432689344	432475132	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	432689344	1967980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432300522	1868863	0	0
T1	5152	702	0	0
T2	256	0	0	0
T3	5006	578	0	0
T4	626	201	0	0
T8	3552	402	0	0
T12	0	10048	0	0
T14	0	2116	0	0
T17	0	934	0	0
T18	12338	0	0	0
T19	6912	0	0	0
T20	2612	0	0	0
T24	2992	0	0	0
T27	0	61	0	0
T33	2084	0	0	0
T39	0	610	0	0
T57	0	259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432689344	432475132	0	0
T1	5152	4970	0	0
T2	4092	3758	0	0
T3	5006	4858	0	0
T4	5860	5538	0	0
T8	3552	3436	0	0
T18	12338	12140	0	0
T19	6912	6738	0	0
T20	2612	2430	0	0
T24	2992	2834	0	0
T33	2084	1920	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432689344	432475132	0	0
T1	5152	4970	0	0
T2	4092	3758	0	0
T3	5006	4858	0	0
T4	5860	5538	0	0
T8	3552	3436	0	0
T18	12338	12140	0	0
T19	6912	6738	0	0
T20	2612	2430	0	0
T24	2992	2834	0	0
T33	2084	1920	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432689344	432475132	0	0
T1	5152	4970	0	0
T2	4092	3758	0	0
T3	5006	4858	0	0
T4	5860	5538	0	0
T8	3552	3436	0	0
T18	12338	12140	0	0
T19	6912	6738	0	0
T20	2612	2430	0	0
T24	2992	2834	0	0
T33	2084	1920	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	432689344	1967980	0	0
T1	5152	702	0	0
T2	4092	407	0	0
T3	5006	578	0	0
T4	5860	3520	0	0
T5	0	2292	0	0
T8	3552	402	0	0
T12	0	10048	0	0
T18	12338	0	0	0
T19	6912	0	0	0
T20	2612	0	0	0
T24	2992	0	0	0
T27	0	61	0	0
T33	2084	0	0	0
T49	0	321	0	0
T57	0	259	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T84,T85
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T86,T87
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T77,T88,T89
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216150261	927296	0	0
DepthKnown_A	216344672	216237566	0	0
RvalidKnown_A	216344672	216237566	0	0
WreadyKnown_A	216344672	216237566	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216344672	976603	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216150261	927296	0	0
T1	2576	357	0	0
T2	128	0	0	0
T3	2503	283	0	0
T4	313	53	0	0
T8	1776	190	0	0
T12	0	5020	0	0
T14	0	1051	0	0
T17	0	405	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T27	0	27	0	0
T33	1042	0	0	0
T39	0	294	0	0
T57	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	976603	0	0
T1	2576	357	0	0
T2	2046	210	0	0
T3	2503	283	0	0
T4	2930	1719	0	0
T5	0	1152	0	0
T8	1776	190	0	0
T12	0	5020	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T27	0	27	0	0
T33	1042	0	0	0
T49	0	165	0	0
T57	0	99	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T80,T82,T83
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T79,T81,T90
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T8,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216150261	941567	0	0
DepthKnown_A	216344672	216237566	0	0
RvalidKnown_A	216344672	216237566	0	0
WreadyKnown_A	216344672	216237566	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216344672	991377	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216150261	941567	0	0
T1	2576	345	0	0
T2	128	0	0	0
T3	2503	295	0	0
T4	313	148	0	0
T8	1776	212	0	0
T12	0	5028	0	0
T14	0	1065	0	0
T17	0	529	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T27	0	34	0	0
T33	1042	0	0	0
T39	0	316	0	0
T57	0	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	991377	0	0
T1	2576	345	0	0
T2	2046	197	0	0
T3	2503	295	0	0
T4	2930	1801	0	0
T5	0	1140	0	0
T8	1776	212	0	0
T12	0	5028	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T27	0	34	0	0
T33	1042	0	0	0
T49	0	156	0	0
T57	0	160	0	0