Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	735083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5992805

1

T1

27

T2

43

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1770632	1			T1	141		T2	132		T3	39
values[0x0]	2290733	1			T1	12		T2	17		T3	8
values[0x1]	2666523	1			T1	15		T2	24		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	360202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6367686

1

T1

63

T2

84

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25885	1			T2	2		T5	1120		T24	1
valid_sources[0x01]	26926	1			T2	1		T28	1		T5	1023
valid_sources[0x02]	26924	1			T5	1090		T11	2		T12	1
valid_sources[0x03]	26139	1			T1	1		T4	6		T5	1045
valid_sources[0x04]	26149	1			T1	1		T2	1		T5	1043
valid_sources[0x05]	27146	1			T3	1		T4	6		T5	1098
valid_sources[0x06]	26233	1			T1	1		T2	3		T28	1
valid_sources[0x07]	24047	1			T4	1		T5	1055		T11	1
valid_sources[0x08]	25852	1			T1	1		T4	4		T5	1089
valid_sources[0x09]	27063	1			T1	1		T2	1		T4	1
valid_sources[0x0a]	24958	1			T5	1045		T11	1		T24	1
valid_sources[0x0b]	27592	1			T1	1		T5	1070		T8	6
valid_sources[0x0c]	24761	1			T5	1171		T24	5		T38	1
valid_sources[0x0d]	27724	1			T1	1		T2	2		T4	1
valid_sources[0x0e]	25939	1			T2	2		T4	12		T5	1110
valid_sources[0x0f]	25643	1			T28	1		T4	5		T5	1089
valid_sources[0x10]	27162	1			T1	1		T2	1		T4	4
valid_sources[0x11]	24554	1			T1	2		T2	1		T4	9
valid_sources[0x12]	27203	1			T4	3		T5	1139		T12	2
valid_sources[0x13]	25928	1			T2	1		T3	1		T5	1133
valid_sources[0x14]	25813	1			T1	4		T2	1		T4	7
valid_sources[0x15]	25344	1			T2	1		T5	1046		T19	17
valid_sources[0x16]	24830	1			T2	1		T4	1		T5	1029
valid_sources[0x17]	26740	1			T4	11		T5	1051		T35	2
valid_sources[0x18]	26030	1			T1	1		T2	2		T4	5
valid_sources[0x19]	26268	1			T2	1		T5	1056		T11	4
valid_sources[0x1a]	25915	1			T1	1		T5	1093		T55	2
valid_sources[0x1b]	26058	1			T4	7		T5	1097		T19	2
valid_sources[0x1c]	27007	1			T1	1		T4	2		T5	1064
valid_sources[0x1d]	24482	1			T4	3		T5	1141		T6	1
valid_sources[0x1e]	27567	1			T3	1		T4	6		T5	1099
valid_sources[0x1f]	27267	1			T1	1		T2	1		T5	1177
valid_sources[0x20]	25211	1			T2	2		T5	1110		T31	2
valid_sources[0x21]	24588	1			T5	1070		T24	1		T54	1
valid_sources[0x22]	26259	1			T4	7		T5	1094		T10	4
valid_sources[0x23]	25249	1			T1	1		T4	4		T5	1085
valid_sources[0x24]	25345	1			T1	2		T2	2		T3	4
valid_sources[0x25]	26737	1			T2	1		T28	2		T4	31
valid_sources[0x26]	26821	1			T1	1		T2	4		T4	4
valid_sources[0x27]	26313	1			T1	1		T4	5		T5	1016
valid_sources[0x28]	25505	1			T2	2		T28	1		T4	7
valid_sources[0x29]	26570	1			T5	1029		T24	4		T54	1
valid_sources[0x2a]	26074	1			T1	1		T2	1		T5	1047
valid_sources[0x2b]	24763	1			T4	5		T5	1067		T12	1
valid_sources[0x2c]	25743	1			T4	7		T5	1052		T32	15
valid_sources[0x2d]	28299	1			T5	1149		T38	1		T57	1
valid_sources[0x2e]	25954	1			T1	1		T4	2		T5	1158
valid_sources[0x2f]	26594	1			T4	7		T5	1039		T10	1
valid_sources[0x30]	26493	1			T5	1078		T57	2		T29	315
valid_sources[0x31]	25603	1			T1	1		T2	1		T4	17
valid_sources[0x32]	25480	1			T1	1		T2	3		T5	1170
valid_sources[0x33]	25929	1			T1	1		T5	1084		T55	2
valid_sources[0x34]	24643	1			T5	1077		T31	2		T24	2
valid_sources[0x35]	26696	1			T5	1055		T9	1		T35	1
valid_sources[0x36]	26880	1			T1	1		T4	10		T5	1090
valid_sources[0x37]	26160	1			T2	1		T28	1		T4	3
valid_sources[0x38]	26242	1			T1	1		T2	1		T3	1
valid_sources[0x39]	27161	1			T1	2		T5	1070		T24	1
valid_sources[0x3a]	26059	1			T4	6		T5	1050		T10	1
valid_sources[0x3b]	27567	1			T1	1		T4	5		T5	1125
valid_sources[0x3c]	26181	1			T4	2		T5	1173		T11	2
valid_sources[0x3d]	25984	1			T1	1		T2	1		T5	1135
valid_sources[0x3e]	26410	1			T2	3		T28	3		T4	21
valid_sources[0x3f]	27797	1			T2	2		T5	1064		T24	2
valid_sources[0x40]	24962	1			T1	1		T5	1109		T33	1
valid_sources[0x41]	27149	1			T1	1		T2	1		T28	1
valid_sources[0x42]	26073	1			T2	2		T4	4		T5	1039
valid_sources[0x43]	27839	1			T1	1		T4	1		T5	1191
valid_sources[0x44]	26592	1			T1	1		T2	1		T5	1139
valid_sources[0x45]	26545	1			T1	1		T5	1085		T10	2
valid_sources[0x46]	26724	1			T1	1		T4	9		T5	1094
valid_sources[0x47]	24739	1			T1	2		T28	5		T4	3
valid_sources[0x48]	25900	1			T4	2		T5	1119		T33	1
valid_sources[0x49]	27500	1			T5	1125		T12	1		T24	2
valid_sources[0x4a]	28372	1			T28	1		T5	1211		T10	4
valid_sources[0x4b]	26883	1			T1	1		T2	1		T28	2
valid_sources[0x4c]	26809	1			T5	1008		T38	1		T25	2
valid_sources[0x4d]	26947	1			T2	2		T5	1076		T10	1
valid_sources[0x4e]	25446	1			T2	2		T28	1		T4	6
valid_sources[0x4f]	27506	1			T5	1130		T11	1		T12	1
valid_sources[0x50]	27425	1			T5	1073		T12	1		T24	1
valid_sources[0x51]	26996	1			T2	2		T5	1063		T24	2
valid_sources[0x52]	25660	1			T2	6		T4	2		T5	1052
valid_sources[0x53]	25300	1			T2	2		T4	2		T5	1095
valid_sources[0x54]	27851	1			T1	1		T2	2		T4	10
valid_sources[0x55]	27683	1			T1	1		T2	1		T4	10
valid_sources[0x56]	25547	1			T1	2		T5	1101		T24	3
valid_sources[0x57]	25410	1			T5	1097		T10	5		T6	1
valid_sources[0x58]	26383	1			T1	1		T2	4		T3	1
valid_sources[0x59]	27048	1			T1	1		T3	4		T5	1047
valid_sources[0x5a]	26538	1			T1	1		T2	3		T28	6
valid_sources[0x5b]	25948	1			T2	2		T5	1092		T11	1
valid_sources[0x5c]	25388	1			T3	10		T4	25		T5	1125
valid_sources[0x5d]	26522	1			T1	2		T28	3		T4	2
valid_sources[0x5e]	26909	1			T1	1		T4	5		T5	1125
valid_sources[0x5f]	25778	1			T1	1		T5	1100		T24	2
valid_sources[0x60]	25651	1			T2	1		T5	1144		T11	1
valid_sources[0x61]	25225	1			T1	2		T5	1074		T24	3
valid_sources[0x62]	26882	1			T5	1097		T12	1		T38	1
valid_sources[0x63]	25740	1			T1	1		T5	1064		T11	2
valid_sources[0x64]	25935	1			T1	1		T4	12		T5	1079
valid_sources[0x65]	25296	1			T2	2		T5	1092		T19	35
valid_sources[0x66]	24770	1			T4	7		T5	1098		T11	1
valid_sources[0x67]	26184	1			T28	1		T4	1		T5	1108
valid_sources[0x68]	28206	1			T1	1		T3	2		T4	3
valid_sources[0x69]	26602	1			T4	1		T5	1135		T34	1
valid_sources[0x6a]	26460	1			T1	1		T2	2		T5	987
valid_sources[0x6b]	27442	1			T1	2		T5	1178		T10	1
valid_sources[0x6c]	26809	1			T2	2		T4	2		T5	1078
valid_sources[0x6d]	27388	1			T1	1		T2	1		T4	4
valid_sources[0x6e]	25409	1			T1	2		T2	3		T4	3
valid_sources[0x6f]	27950	1			T1	3		T5	1053		T34	1
valid_sources[0x70]	26263	1			T28	2		T4	8		T5	1049
valid_sources[0x71]	25762	1			T4	2		T5	1083		T12	1
valid_sources[0x72]	25822	1			T1	1		T4	7		T5	1078
valid_sources[0x73]	27787	1			T1	2		T2	1		T28	1
valid_sources[0x74]	25637	1			T1	1		T5	1116		T31	5
valid_sources[0x75]	25703	1			T5	1013		T24	2		T38	1
valid_sources[0x76]	24193	1			T28	1		T4	2		T5	1004
valid_sources[0x77]	26217	1			T5	1128		T24	1		T38	2
valid_sources[0x78]	26567	1			T2	2		T5	1143		T54	1
valid_sources[0x79]	25612	1			T1	2		T4	9		T5	1106
valid_sources[0x7a]	26737	1			T1	1		T2	1		T28	2
valid_sources[0x7b]	25671	1			T2	1		T5	1041		T24	2
valid_sources[0x7c]	26924	1			T1	3		T28	3		T4	7
valid_sources[0x7d]	26053	1			T1	1		T2	1		T4	1
valid_sources[0x7e]	24699	1			T2	1		T5	1016		T31	5
valid_sources[0x7f]	26755	1			T4	9		T5	1137		T24	3
valid_sources[0x80]	24937	1			T4	10		T5	1100		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1508890

1

T1

3

T2

3

T3

6

values[0x0]

all_enables

biggest_size

2243851

1

T1

12

T2

17

T3

7

values[0x1]

all_enables

biggest_size

2240064

1

T1

12

T2

23

T3

8