Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.94	60.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	60.94	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.94	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	25	27	51.92

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	25	27	51.92	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2789	1			T2	1		T3	2		T28	1
non_zero_bins[1]	2080	1			T1	2		T2	2		T28	2
zero	9888	1			T1	2		T2	4		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	593	1			T4	3		T5	10		T42	1
uni	3942	1			T1	1		T2	2		T3	2
gen	4632	1			T1	1		T2	2		T3	1
res	905	1			T1	1		T2	1		T28	1
ins	4685	1			T1	1		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9868

1

T1

3

T2

6

T3

5

mubi_true

4889

1

T1

1

T2

1

T28

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

17

1

T12

1

T70

1

T287

1

pass

14740

1

T1

4

T2

7

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	25	27	51.92	25
Automatically Generated Cross Bins	52	25	27	51.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4
[res , ins]	*	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen]	[zero]	[fail]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	149	1			T5	3		T30	1		T135	4
upd	non_zero_bins[0]	pass	mubi_true	146	1			T4	2		T5	1		T42	1
upd	non_zero_bins[1]	pass	mubi_false	81	1			T5	1		T39	1		T30	1
upd	non_zero_bins[1]	pass	mubi_true	99	1			T4	1		T5	2		T29	1
upd	zero	pass	mubi_false	57	1			T249	1		T30	1		T135	2
upd	zero	pass	mubi_true	61	1			T5	3		T35	1		T29	1
uni	zero	pass	mubi_false	2961	1			T1	1		T2	2		T3	2
uni	zero	pass	mubi_true	981	1			T4	2		T5	23		T42	7
gen	non_zero_bins[0]	pass	mubi_false	510	1			T2	1		T3	1		T5	10
gen	non_zero_bins[0]	pass	mubi_true	510	1			T4	1		T5	7		T11	1
gen	non_zero_bins[1]	pass	mubi_false	375	1			T1	1		T4	2		T5	6
gen	non_zero_bins[1]	pass	mubi_true	399	1			T28	1		T4	1		T5	5
gen	zero	fail	mubi_false	17	1			T12	1		T70	1		T287	1
gen	zero	pass	mubi_false	2068	1			T2	1		T4	3		T5	33
gen	zero	pass	mubi_true	753	1			T5	7		T19	2		T12	2
res	non_zero_bins[0]	pass	mubi_false	203	1			T5	2		T10	2		T42	2
res	non_zero_bins[0]	pass	mubi_true	190	1			T28	1		T131	1		T29	1
res	non_zero_bins[1]	pass	mubi_false	173	1			T2	1		T5	2		T31	1
res	non_zero_bins[1]	pass	mubi_true	130	1			T21	1		T296	1		T29	1
res	zero	pass	mubi_false	119	1			T5	2		T11	2		T32	1
res	zero	pass	mubi_true	90	1			T1	1		T24	2		T297	1
ins	non_zero_bins[0]	pass	mubi_false	550	1			T3	1		T4	1		T5	17
ins	non_zero_bins[0]	pass	mubi_true	531	1			T4	2		T5	16		T10	1
ins	non_zero_bins[1]	pass	mubi_false	424	1			T1	1		T28	1		T4	1
ins	non_zero_bins[1]	pass	mubi_true	399	1			T2	1		T4	2		T5	10
ins	zero	pass	mubi_false	2181	1			T2	1		T3	1		T4	2
ins	zero	pass	mubi_true	600	1			T4	1		T5	9		T33	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded