Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T58,T68
1	1	Covered	T2,T33,T19

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T19,T12
1	1	Covered	T10,T11,T12

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T12,T26
1	0	Covered	T6,T7,T8

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T19,T12,T26
1	Covered	T6,T7,T8

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T19,T12,T26
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T6,T19,T12
1	Covered	T6,T7,T8

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T11,T12
AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoCaptReseedCnt	141	Covered	T10,T11,T24
AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns	69	Covered	T10,T11,T12
AutoSendGenCmd	150	Covered	T10,T11,T12
AutoSendReseedCmd	162	Covered	T10,T11,T24
BootDone	98	Covered	T2,T33,T32
BootGenAckWait	90	Covered	T2,T33,T32
BootInsAckWait	80	Covered	T2,T33,T19
BootLoadGen	85	Covered	T2,T33,T32
BootLoadIns	65	Covered	T2,T33,T19
BootLoadUni	102	Covered	T2,T32,T26
BootPulse	94	Covered	T2,T33,T32
BootUniAckWait	107	Covered	T2,T32,T26
Error	188	Covered	T6,T7,T8
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T19,T12,T26
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T11,T24
AutoAckWait->Error	188	Covered	T106,T145,T146
AutoAckWait->Idle	211	Covered	T10,T21,T22
AutoAckWait->RejectCsrngEntropy	188	Covered	T12,T26,T132
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T11,T12
AutoCaptGenCnt->Error	188	Covered	T17,T147
AutoCaptGenCnt->Idle	211	Covered	T99,T101,T129
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T148,T149,T150
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T11,T24
AutoCaptReseedCnt->Error	188	Covered	T151,T152,T153
AutoCaptReseedCnt->Idle	211	Covered	T154,T155,T156
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T157,T158,T159
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T11,T24
AutoDispatch->Error	188	Covered	T160,T161
AutoDispatch->Idle	138	Covered	T11,T24,T20
AutoDispatch->RejectCsrngEntropy	188	Covered	T162,T163,T164
AutoFirstAckWait->AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait->Error	188	Covered	T102,T103
AutoFirstAckWait->Idle	211	Covered	T10,T21,T22
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T165,T166,T167
AutoLoadIns->AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns->Error	188	Covered	T8,T16,T168
AutoLoadIns->Idle	211	Covered	T7,T8,T132
AutoLoadIns->RejectCsrngEntropy	188	Covered	T40,T169,T170
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T11,T12
AutoSendGenCmd->Error	188	Covered	T7,T9,T112
AutoSendGenCmd->Idle	211	Covered	T100,T114,T115
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T171,T172,T173
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T11,T24
AutoSendReseedCmd->Error	188	Covered	T174,T175,T176
AutoSendReseedCmd->Idle	211	Covered	T177,T178,T179
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T180,T141,T181
BootDone->BootLoadUni	102	Covered	T2,T32,T26
BootDone->Error	188	Covered	T49,T182,T183
BootDone->Idle	211	Covered	T184,T185,T186
BootDone->RejectCsrngEntropy	188	Covered	T61,T187,T188
BootGenAckWait->BootPulse	94	Covered	T2,T33,T32
BootGenAckWait->Error	188	Covered	T44,T117,T48
BootGenAckWait->Idle	211	Covered	T116,T105,T189
BootGenAckWait->RejectCsrngEntropy	188	Covered	T71,T190,T143
BootInsAckWait->BootLoadGen	85	Covered	T2,T33,T32
BootInsAckWait->Error	188	Covered	T191,T192
BootInsAckWait->Idle	211	Covered	T58,T68,T64
BootInsAckWait->RejectCsrngEntropy	188	Covered	T19,T139,T62
BootLoadGen->BootGenAckWait	90	Covered	T2,T33,T32
BootLoadGen->Error	188	Covered	T193,T194
BootLoadGen->Idle	211	Covered	T33,T66,T104
BootLoadGen->RejectCsrngEntropy	188	Covered	T69,T195,T196
BootLoadIns->BootInsAckWait	80	Covered	T2,T33,T19
BootLoadIns->Error	188	Covered	T18,T197,T198
BootLoadIns->Idle	211	Covered	T50,T199,T200
BootLoadIns->RejectCsrngEntropy	188	Covered	T201,T202,T203
BootLoadUni->BootUniAckWait	107	Covered	T2,T32,T26
BootLoadUni->Error	188	Covered	T116
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T136,T204,T205
BootPulse->BootDone	98	Covered	T2,T33,T32
BootPulse->Error	188	Covered	T206,T207
BootPulse->Idle	211	Covered	T91,T208,T207
BootPulse->RejectCsrngEntropy	188	Covered	T209,T210,T211
BootUniAckWait->Error	188	Covered	T111,T212,T213
BootUniAckWait->Idle	112	Covered	T2,T32,T26
BootUniAckWait->RejectCsrngEntropy	188	Covered	T67,T37,T214
Idle->AutoLoadIns	69	Covered	T10,T11,T12
Idle->BootLoadIns	65	Covered	T2,T33,T19
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T19,T26,T62
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T215,T216,T126
RejectCsrngEntropy->Idle	211	Covered	T19,T12,T26
SWPortMode->Error	188	Covered	T59,T98,T43
SWPortMode->Idle	211	Covered	T4,T5,T19
SWPortMode->RejectCsrngEntropy	188	Covered	T12,T132,T139

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T19
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T19
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T19
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T19
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T32
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T32
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T32
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T32
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T32,T26
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T33,T26,T58
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T32,T26
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T32,T67
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T32,T26
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T11,T12
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T11,T24,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T11,T24
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T11,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T11,T12
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T24
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T11,T24
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T24,T20
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T12,T26
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T58,T94

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T6,T7,T8
1	0	1	-	Not Covered
1	0	0	-	Covered	T19,T12,T26
0	-	-	1	Covered	T10,T33,T19
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	235601321	86275	0	0
FpvSecCmErrorStEscalate_A	235601321	86404	0	0
u_state_regs_A	235567870	235463122	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	86275	0	0
T6	1221	619	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1105	0	0
T59	0	1124	0	0
T94	0	1020	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	86404	0	0
T6	1221	620	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1106	0	0
T59	0	1125	0	0
T94	0	1021	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235567870	235463122	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0