Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T28
DataWait	75	Covered	T1,T3,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T91,T92,T93
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T28
DataWait->AckPls	80	Covered	T1,T3,T28
DataWait->Disabled	107	Covered	T33,T64,T66
DataWait->Error	99	Covered	T58,T17,T94
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T28
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T7,T8

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T28
Idle	-	1	0	-	Covered	T1,T3,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T28
DataWait	-	-	-	0	Covered	T1,T3,T28
AckPls	-	-	-	-	Covered	T1,T3,T28
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1649209247	617275	0	0
FpvSecCmErrorStEscalate_A	1649209247	618178	0	0
u_state_regs_A	1649175796	1648442560	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649209247	617275	0	0
T6	8547	4683	0	0
T7	13622	5319	0	0
T8	0	8049	0	0
T9	0	4451	0	0
T12	17437	0	0	0
T16	0	4214	0	0
T17	0	4417	0	0
T19	14028	0	0	0
T20	34881	0	0	0
T21	15001	0	0	0
T24	44373	0	0	0
T27	4102	0	0	0
T32	10115	0	0	0
T38	14672	0	0	0
T58	0	8085	0	0
T59	0	7818	0	0
T94	0	7490	0	0
T98	0	6740	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649209247	618178	0	0
T6	8547	4690	0	0
T7	13622	5326	0	0
T8	0	8056	0	0
T9	0	4458	0	0
T12	17437	0	0	0
T16	0	4221	0	0
T17	0	4424	0	0
T19	14028	0	0	0
T20	34881	0	0	0
T21	15001	0	0	0
T24	44373	0	0	0
T27	4102	0	0	0
T32	10115	0	0	0
T38	14672	0	0	0
T58	0	8092	0	0
T59	0	7825	0	0
T94	0	7497	0	0
T98	0	6747	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1649175796	1648442560	0	0
T1	31143	30471	0	0
T2	27013	26376	0	0
T3	12075	11522	0	0
T4	119945	116172	0	0
T5	5561066	5561003	0	0
T10	16128	15638	0	0
T11	43323	42777	0	0
T28	19005	18347	0	0
T33	8260	7903	0	0
T41	9016	8449	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T31,T32
DataWait	75	Covered	T1,T31,T32
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T31,T32
DataWait->AckPls	80	Covered	T1,T31,T32
DataWait->Disabled	107	Covered	T99,T100,T101
DataWait->Error	99	Covered	T102,T103
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T31,T32
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T31,T32
Idle	-	1	0	-	Covered	T1,T31,T32
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T31,T32
DataWait	-	-	-	0	Covered	T1,T31,T32
AckPls	-	-	-	-	Covered	T1,T31,T32
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	88475	0	0
FpvSecCmErrorStEscalate_A	235601321	88604	0	0
u_state_regs_A	235601321	235496573	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88475	0	0
T6	1221	669	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1124	0	0
T94	0	1070	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88604	0	0
T6	1221	670	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1125	0	0
T94	0	1071	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T31,T19
DataWait	75	Covered	T1,T31,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T31,T19
DataWait->AckPls	80	Covered	T1,T31,T19
DataWait->Disabled	107	Covered	T64,T104,T105
DataWait->Error	99	Covered	T17,T44,T106
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T31,T19
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T31,T19
Idle	-	1	0	-	Covered	T1,T31,T6
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T31,T19
DataWait	-	-	-	0	Covered	T1,T31,T19
AckPls	-	-	-	-	Covered	T1,T31,T19
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	88475	0	0
FpvSecCmErrorStEscalate_A	235601321	88604	0	0
u_state_regs_A	235601321	235496573	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88475	0	0
T6	1221	669	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1124	0	0
T94	0	1070	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88604	0	0
T6	1221	670	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1125	0	0
T94	0	1071	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T31,T24
DataWait	75	Covered	T1,T31,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T31,T24
DataWait->AckPls	80	Covered	T1,T31,T24
DataWait->Disabled	107	Covered	T107,T108,T109
DataWait->Error	99	Covered	T110,T111,T112
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T31,T24
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T31,T24
Idle	-	1	0	-	Covered	T1,T31,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T31,T24
DataWait	-	-	-	0	Covered	T1,T31,T24
AckPls	-	-	-	-	Covered	T1,T31,T24
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	88475	0	0
FpvSecCmErrorStEscalate_A	235601321	88604	0	0
u_state_regs_A	235601321	235496573	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88475	0	0
T6	1221	669	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1124	0	0
T94	0	1070	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88604	0	0
T6	1221	670	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1125	0	0
T94	0	1071	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T31,T32
DataWait	75	Covered	T1,T31,T32
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T31,T32
DataWait->AckPls	80	Covered	T1,T31,T32
DataWait->Disabled	107	Covered	T113,T114,T115
DataWait->Error	99	Covered	T7,T116,T117
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T31,T32
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T31,T32
Idle	-	1	0	-	Covered	T1,T31,T32
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T31,T32
DataWait	-	-	-	0	Covered	T1,T31,T32
AckPls	-	-	-	-	Covered	T1,T31,T32
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	88475	0	0
FpvSecCmErrorStEscalate_A	235601321	88604	0	0
u_state_regs_A	235601321	235496573	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88475	0	0
T6	1221	669	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1124	0	0
T94	0	1070	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88604	0	0
T6	1221	670	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1125	0	0
T94	0	1071	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T28
DataWait	75	Covered	T1,T3,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T28
DataWait->AckPls	80	Covered	T1,T3,T28
DataWait->Disabled	107	Covered	T118,T119,T120
DataWait->Error	99	Covered	T58,T94,T121
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T28
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T17,T122

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T28
Idle	-	1	0	-	Covered	T1,T3,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T28
DataWait	-	-	-	0	Covered	T1,T3,T28
AckPls	-	-	-	-	Covered	T1,T3,T28
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	86425	0	0
FpvSecCmErrorStEscalate_A	235601321	86554	0	0
u_state_regs_A	235567870	235463122	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	86425	0	0
T6	1221	669	0	0
T7	1946	717	0	0
T8	0	1107	0	0
T9	0	593	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1074	0	0
T94	0	1070	0	0
T98	0	920	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	86554	0	0
T6	1221	670	0	0
T7	1946	718	0	0
T8	0	1108	0	0
T9	0	594	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1075	0	0
T94	0	1071	0	0
T98	0	921	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235567870	235463122	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T31,T32
DataWait	75	Covered	T1,T31,T32
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T91,T93
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T31,T32
DataWait->AckPls	80	Covered	T1,T31,T32
DataWait->Disabled	107	Covered	T123,T124,T125
DataWait->Error	99	Covered	T126,T127,T128
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T31,T32
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T31,T32
Idle	-	1	0	-	Covered	T1,T31,T32
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T31,T32
DataWait	-	-	-	0	Covered	T1,T31,T32
AckPls	-	-	-	-	Covered	T1,T31,T32
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	88475	0	0
FpvSecCmErrorStEscalate_A	235601321	88604	0	0
u_state_regs_A	235601321	235496573	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88475	0	0
T6	1221	669	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1124	0	0
T94	0	1070	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88604	0	0
T6	1221	670	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1125	0	0
T94	0	1071	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T33,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T33
DataWait	75	Covered	T1,T2,T33
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T6,T7,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T92
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T33
DataWait->AckPls	80	Covered	T1,T2,T33
DataWait->Disabled	107	Covered	T33,T66,T129
DataWait->Error	99	Covered	T48
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T50,T95,T96
EndPointClear->Error	99	Covered	T16,T18,T97
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T33
Idle->Disabled	107	Covered	T4,T5,T10
Idle->Error	99	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T33
Idle	-	1	0	-	Covered	T1,T2,T33
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T33
DataWait	-	-	-	0	Covered	T1,T2,T33
AckPls	-	-	-	-	Covered	T1,T2,T33
Error	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T10,T33,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	235601321	88475	0	0
FpvSecCmErrorStEscalate_A	235601321	88604	0	0
u_state_regs_A	235601321	235496573	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88475	0	0
T6	1221	669	0	0
T7	1946	767	0	0
T8	0	1157	0	0
T9	0	643	0	0
T12	2491	0	0	0
T16	0	602	0	0
T17	0	631	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1155	0	0
T59	0	1124	0	0
T94	0	1070	0	0
T98	0	970	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	88604	0	0
T6	1221	670	0	0
T7	1946	768	0	0
T8	0	1158	0	0
T9	0	644	0	0
T12	2491	0	0	0
T16	0	603	0	0
T17	0	632	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	0	0	0
T32	1445	0	0	0
T38	2096	0	0	0
T58	0	1156	0	0
T59	0	1125	0	0
T94	0	1071	0	0
T98	0	971	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0