Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T27,T76,T83
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T79,T81
1	0	1	Covered	T10,T11,T6
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470847544	1479267	0	0
DepthKnown_A	471202642	470993146	0	0
RvalidKnown_A	471202642	470993146	0	0
WreadyKnown_A	471202642	470993146	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	471202642	1551874	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470847544	1479267	0	0
T6	192	0	0	0
T7	0	205	0	0
T8	0	407	0	0
T10	4608	2187	0	0
T11	12378	10473	0	0
T12	4982	611	0	0
T19	4008	75	0	0
T20	0	6645	0	0
T21	0	2817	0	0
T24	12678	6405	0	0
T26	0	720	0	0
T31	7764	0	0	0
T32	2890	0	0	0
T33	2360	0	0	0
T41	2576	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471202642	470993146	0	0
T1	8898	8706	0	0
T2	7718	7536	0	0
T3	3450	3292	0	0
T4	34270	33192	0	0
T5	1588876	1588858	0	0
T10	4608	4468	0	0
T11	12378	12222	0	0
T28	5430	5242	0	0
T33	2360	2258	0	0
T41	2576	2414	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471202642	470993146	0	0
T1	8898	8706	0	0
T2	7718	7536	0	0
T3	3450	3292	0	0
T4	34270	33192	0	0
T5	1588876	1588858	0	0
T10	4608	4468	0	0
T11	12378	12222	0	0
T28	5430	5242	0	0
T33	2360	2258	0	0
T41	2576	2414	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471202642	470993146	0	0
T1	8898	8706	0	0
T2	7718	7536	0	0
T3	3450	3292	0	0
T4	34270	33192	0	0
T5	1588876	1588858	0	0
T10	4608	4468	0	0
T11	12378	12222	0	0
T28	5430	5242	0	0
T33	2360	2258	0	0
T41	2576	2414	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	471202642	1551874	0	0
T6	2442	309	0	0
T7	0	1595	0	0
T10	4608	2187	0	0
T11	12378	10473	0	0
T12	4982	611	0	0
T19	4008	75	0	0
T20	0	6645	0	0
T21	0	2817	0	0
T24	12678	6405	0	0
T26	0	361	0	0
T27	0	33	0	0
T31	7764	0	0	0
T32	2890	0	0	0
T33	2360	0	0	0
T41	2576	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T84,T85
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T76,T83
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T81,T86,T87
1	0	1	Covered	T10,T11,T6
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	235423772	733606	0	0
DepthKnown_A	235601321	235496573	0	0
RvalidKnown_A	235601321	235496573	0	0
WreadyKnown_A	235601321	235496573	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	235601321	770037	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235423772	733606	0	0
T6	96	0	0	0
T7	0	59	0	0
T8	0	152	0	0
T10	2304	1036	0	0
T11	6189	5225	0	0
T12	2491	303	0	0
T19	2004	29	0	0
T20	0	3299	0	0
T21	0	1379	0	0
T24	6339	3189	0	0
T26	0	361	0	0
T31	3882	0	0	0
T32	1445	0	0	0
T33	1180	0	0	0
T41	1288	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	770037	0	0
T6	1221	160	0	0
T7	0	800	0	0
T10	2304	1036	0	0
T11	6189	5225	0	0
T12	2491	303	0	0
T19	2004	29	0	0
T20	0	3299	0	0
T21	0	1379	0	0
T24	6339	3189	0	0
T26	0	361	0	0
T31	3882	0	0	0
T32	1445	0	0	0
T33	1180	0	0	0
T41	1288	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T27
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T79,T88
1	0	1	Covered	T10,T11,T6
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	235423772	745661	0	0
DepthKnown_A	235601321	235496573	0	0
RvalidKnown_A	235601321	235496573	0	0
WreadyKnown_A	235601321	235496573	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	235601321	781837	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235423772	745661	0	0
T6	96	0	0	0
T7	0	146	0	0
T8	0	255	0	0
T10	2304	1151	0	0
T11	6189	5248	0	0
T12	2491	308	0	0
T19	2004	46	0	0
T20	0	3346	0	0
T21	0	1438	0	0
T24	6339	3216	0	0
T26	0	359	0	0
T31	3882	0	0	0
T32	1445	0	0	0
T33	1180	0	0	0
T41	1288	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	781837	0	0
T6	1221	149	0	0
T7	0	795	0	0
T10	2304	1151	0	0
T11	6189	5248	0	0
T12	2491	308	0	0
T19	2004	46	0	0
T20	0	3346	0	0
T21	0	1438	0	0
T24	6339	3216	0	0
T27	0	33	0	0
T31	3882	0	0	0
T32	1445	0	0	0
T33	1180	0	0	0
T41	1288	0	0	0