Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T10 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T12,T21 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T37,T137,T214 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T3,T28 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1884810568 |
210571807 |
0 |
7680 |
| T1 |
35592 |
5533 |
0 |
8 |
| T2 |
30872 |
0 |
0 |
8 |
| T3 |
13800 |
1280 |
0 |
8 |
| T4 |
137080 |
1804 |
0 |
8 |
| T5 |
6355504 |
594418 |
0 |
8 |
| T10 |
18432 |
620 |
0 |
8 |
| T11 |
49512 |
2960 |
0 |
8 |
| T12 |
0 |
1475 |
0 |
0 |
| T13 |
0 |
4142 |
0 |
0 |
| T20 |
0 |
3954 |
0 |
0 |
| T21 |
0 |
618 |
0 |
0 |
| T24 |
0 |
4873 |
0 |
0 |
| T26 |
0 |
1719 |
0 |
0 |
| T28 |
21720 |
1175 |
0 |
8 |
| T31 |
0 |
6799 |
0 |
0 |
| T32 |
0 |
2224 |
0 |
0 |
| T33 |
9440 |
0 |
0 |
8 |
| T34 |
0 |
3536 |
0 |
0 |
| T35 |
0 |
1424 |
0 |
0 |
| T38 |
0 |
1307 |
0 |
0 |
| T40 |
0 |
1482 |
0 |
0 |
| T41 |
10304 |
0 |
0 |
8 |
| T60 |
0 |
1318 |
0 |
0 |
| T62 |
0 |
1520 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1884810568 |
210571807 |
0 |
0 |
| T1 |
35592 |
5533 |
0 |
0 |
| T2 |
30872 |
0 |
0 |
0 |
| T3 |
13800 |
1280 |
0 |
0 |
| T4 |
137080 |
1804 |
0 |
0 |
| T5 |
6355504 |
594418 |
0 |
0 |
| T10 |
18432 |
620 |
0 |
0 |
| T11 |
49512 |
2960 |
0 |
0 |
| T12 |
0 |
1475 |
0 |
0 |
| T13 |
0 |
4142 |
0 |
0 |
| T20 |
0 |
3954 |
0 |
0 |
| T21 |
0 |
618 |
0 |
0 |
| T24 |
0 |
4873 |
0 |
0 |
| T26 |
0 |
1719 |
0 |
0 |
| T28 |
21720 |
1175 |
0 |
0 |
| T31 |
0 |
6799 |
0 |
0 |
| T32 |
0 |
2224 |
0 |
0 |
| T33 |
9440 |
0 |
0 |
0 |
| T34 |
0 |
3536 |
0 |
0 |
| T35 |
0 |
1424 |
0 |
0 |
| T38 |
0 |
1307 |
0 |
0 |
| T40 |
0 |
1482 |
0 |
0 |
| T41 |
10304 |
0 |
0 |
0 |
| T60 |
0 |
1318 |
0 |
0 |
| T62 |
0 |
1520 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T10 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T12,T21 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
12 |
85.71 |
| TERNARY |
142 |
4 |
3 |
75.00 |
| TERNARY |
147 |
3 |
2 |
66.67 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
164938 |
0 |
960 |
| T1 |
4449 |
7 |
0 |
1 |
| T2 |
3859 |
8 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T10 |
2304 |
469 |
0 |
1 |
| T11 |
6189 |
853 |
0 |
1 |
| T20 |
0 |
430 |
0 |
0 |
| T21 |
0 |
533 |
0 |
0 |
| T24 |
0 |
340 |
0 |
0 |
| T27 |
0 |
74 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
14 |
0 |
0 |
| T32 |
0 |
5 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T41 |
1288 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
164938 |
0 |
0 |
| T1 |
4449 |
7 |
0 |
0 |
| T2 |
3859 |
8 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T10 |
2304 |
469 |
0 |
0 |
| T11 |
6189 |
853 |
0 |
0 |
| T20 |
0 |
430 |
0 |
0 |
| T21 |
0 |
533 |
0 |
0 |
| T24 |
0 |
340 |
0 |
0 |
| T27 |
0 |
74 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
14 |
0 |
0 |
| T32 |
0 |
5 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T137,T214,T217 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T3,T28 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T3,T28 |
| 0 |
0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
208347806 |
0 |
960 |
| T1 |
4449 |
1593 |
0 |
1 |
| T2 |
3859 |
0 |
0 |
1 |
| T3 |
1725 |
1280 |
0 |
1 |
| T4 |
17135 |
1804 |
0 |
1 |
| T5 |
794438 |
594418 |
0 |
1 |
| T10 |
2304 |
620 |
0 |
1 |
| T11 |
6189 |
2960 |
0 |
1 |
| T12 |
0 |
1475 |
0 |
0 |
| T24 |
0 |
4873 |
0 |
0 |
| T28 |
2715 |
1175 |
0 |
1 |
| T31 |
0 |
2336 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T41 |
1288 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
208347806 |
0 |
0 |
| T1 |
4449 |
1593 |
0 |
0 |
| T2 |
3859 |
0 |
0 |
0 |
| T3 |
1725 |
1280 |
0 |
0 |
| T4 |
17135 |
1804 |
0 |
0 |
| T5 |
794438 |
594418 |
0 |
0 |
| T10 |
2304 |
620 |
0 |
0 |
| T11 |
6189 |
2960 |
0 |
0 |
| T12 |
0 |
1475 |
0 |
0 |
| T24 |
0 |
4873 |
0 |
0 |
| T28 |
2715 |
1175 |
0 |
0 |
| T31 |
0 |
2336 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T31,T32 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T32 |
| 1 | 0 | Covered | T1,T31,T32 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T31,T32 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T187,T218,T186 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T31,T32 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T31,T32 |
| 0 |
0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
265775 |
0 |
960 |
| T1 |
4449 |
2024 |
0 |
1 |
| T2 |
3859 |
0 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T10 |
2304 |
0 |
0 |
1 |
| T11 |
6189 |
0 |
0 |
1 |
| T13 |
0 |
1676 |
0 |
0 |
| T21 |
0 |
618 |
0 |
0 |
| T26 |
0 |
1719 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
2156 |
0 |
0 |
| T32 |
0 |
1337 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T34 |
0 |
1716 |
0 |
0 |
| T35 |
0 |
1424 |
0 |
0 |
| T40 |
0 |
1482 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
1 |
| T60 |
0 |
1318 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
265775 |
0 |
0 |
| T1 |
4449 |
2024 |
0 |
0 |
| T2 |
3859 |
0 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
0 |
| T11 |
6189 |
0 |
0 |
0 |
| T13 |
0 |
1676 |
0 |
0 |
| T21 |
0 |
618 |
0 |
0 |
| T26 |
0 |
1719 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
2156 |
0 |
0 |
| T32 |
0 |
1337 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T34 |
0 |
1716 |
0 |
0 |
| T35 |
0 |
1424 |
0 |
0 |
| T40 |
0 |
1482 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
| T60 |
0 |
1318 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T31,T32 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T32 |
| 1 | 0 | Covered | T1,T31,T32 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T31,T32 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T37,T136,T180 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T31,T32 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T31,T32 |
| 0 |
0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
468287 |
0 |
960 |
| T1 |
4449 |
1916 |
0 |
1 |
| T2 |
3859 |
0 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T10 |
2304 |
0 |
0 |
1 |
| T11 |
6189 |
0 |
0 |
1 |
| T13 |
0 |
2466 |
0 |
0 |
| T20 |
0 |
3954 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
2307 |
0 |
0 |
| T32 |
0 |
887 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T34 |
0 |
1820 |
0 |
0 |
| T36 |
0 |
1015 |
0 |
0 |
| T38 |
0 |
1307 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
1 |
| T53 |
0 |
1445 |
0 |
0 |
| T62 |
0 |
1520 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
468287 |
0 |
0 |
| T1 |
4449 |
1916 |
0 |
0 |
| T2 |
3859 |
0 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
0 |
| T11 |
6189 |
0 |
0 |
0 |
| T13 |
0 |
2466 |
0 |
0 |
| T20 |
0 |
3954 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
2307 |
0 |
0 |
| T32 |
0 |
887 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T34 |
0 |
1820 |
0 |
0 |
| T36 |
0 |
1015 |
0 |
0 |
| T38 |
0 |
1307 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
| T53 |
0 |
1445 |
0 |
0 |
| T62 |
0 |
1520 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T31,T19 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T19 |
| 1 | 0 | Covered | T1,T31,T19 |
| 1 | 1 | Covered | T1,T31,T19 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T19 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T31,T19 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T31,T19 |
| 1 | 1 | Covered | T1,T31,T19 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T19 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T19 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T19 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T19 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T19 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T219,T188,T220 |
| 1 | 1 | Covered | T1,T31,T19 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T31,T19 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T31,T19 |
| 0 |
0 |
1 |
Covered |
T1,T31,T19 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T19 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
466525 |
0 |
960 |
| T1 |
4449 |
1575 |
0 |
1 |
| T2 |
3859 |
0 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T10 |
2304 |
0 |
0 |
1 |
| T11 |
6189 |
0 |
0 |
1 |
| T13 |
0 |
2437 |
0 |
0 |
| T19 |
0 |
1228 |
0 |
0 |
| T24 |
0 |
4435 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
2274 |
0 |
0 |
| T32 |
0 |
925 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T38 |
0 |
1281 |
0 |
0 |
| T39 |
0 |
1161 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
1 |
| T64 |
0 |
936 |
0 |
0 |
| T65 |
0 |
1481 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
466525 |
0 |
0 |
| T1 |
4449 |
1575 |
0 |
0 |
| T2 |
3859 |
0 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
0 |
| T11 |
6189 |
0 |
0 |
0 |
| T13 |
0 |
2437 |
0 |
0 |
| T19 |
0 |
1228 |
0 |
0 |
| T24 |
0 |
4435 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
2274 |
0 |
0 |
| T32 |
0 |
925 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T38 |
0 |
1281 |
0 |
0 |
| T39 |
0 |
1161 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
| T64 |
0 |
936 |
0 |
0 |
| T65 |
0 |
1481 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T33 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T33 |
| 1 | 0 | Covered | T1,T2,T33 |
| 1 | 1 | Covered | T1,T2,T33 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T33 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T33 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T33 |
| 1 | 1 | Covered | T1,T2,T33 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T33 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T33 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T33 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T33 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T184,T221 |
| 1 | 1 | Covered | T1,T2,T33 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T33 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T33 |
| 0 |
0 |
1 |
Covered |
T1,T2,T33 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T33 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T33 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
295717 |
0 |
960 |
| T1 |
4449 |
2087 |
0 |
1 |
| T2 |
3859 |
2111 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T10 |
2304 |
0 |
0 |
1 |
| T11 |
6189 |
0 |
0 |
1 |
| T20 |
0 |
2022 |
0 |
0 |
| T26 |
0 |
125 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
2252 |
0 |
0 |
| T33 |
1180 |
1006 |
0 |
1 |
| T34 |
0 |
1580 |
0 |
0 |
| T39 |
0 |
1476 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
1 |
| T50 |
0 |
1148 |
0 |
0 |
| T59 |
0 |
1138 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
295717 |
0 |
0 |
| T1 |
4449 |
2087 |
0 |
0 |
| T2 |
3859 |
2111 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
0 |
| T11 |
6189 |
0 |
0 |
0 |
| T20 |
0 |
2022 |
0 |
0 |
| T26 |
0 |
125 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
2252 |
0 |
0 |
| T33 |
1180 |
1006 |
0 |
0 |
| T34 |
0 |
1580 |
0 |
0 |
| T39 |
0 |
1476 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
| T50 |
0 |
1148 |
0 |
0 |
| T59 |
0 |
1138 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T31,T24 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T24 |
| 1 | 0 | Covered | T1,T31,T24 |
| 1 | 1 | Covered | T1,T31,T24 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T24 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T31,T24 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T31,T24 |
| 1 | 1 | Covered | T1,T31,T24 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T24 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T24 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T24 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T24 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T24 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T67,T61,T205 |
| 1 | 1 | Covered | T1,T31,T24 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T31,T24 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T31,T24 |
| 0 |
0 |
1 |
Covered |
T1,T31,T24 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T24 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T24 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
398836 |
0 |
960 |
| T1 |
4449 |
1538 |
0 |
1 |
| T2 |
3859 |
0 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T10 |
2304 |
0 |
0 |
1 |
| T11 |
6189 |
0 |
0 |
1 |
| T13 |
0 |
1747 |
0 |
0 |
| T20 |
0 |
3876 |
0 |
0 |
| T24 |
0 |
2062 |
0 |
0 |
| T27 |
0 |
124 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
2249 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T39 |
0 |
1468 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
1 |
| T53 |
0 |
1417 |
0 |
0 |
| T67 |
0 |
1200 |
0 |
0 |
| T68 |
0 |
416 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
398836 |
0 |
0 |
| T1 |
4449 |
1538 |
0 |
0 |
| T2 |
3859 |
0 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
0 |
| T11 |
6189 |
0 |
0 |
0 |
| T13 |
0 |
1747 |
0 |
0 |
| T20 |
0 |
3876 |
0 |
0 |
| T24 |
0 |
2062 |
0 |
0 |
| T27 |
0 |
124 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
2249 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T39 |
0 |
1468 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
| T53 |
0 |
1417 |
0 |
0 |
| T67 |
0 |
1200 |
0 |
0 |
| T68 |
0 |
416 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T31,T32 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T32 |
| 1 | 0 | Covered | T1,T31,T32 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T31,T32 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T31,T32 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T31,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T222,T223,T224 |
| 1 | 1 | Covered | T1,T31,T32 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T31,T32 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T31,T32 |
| 0 |
0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
163923 |
0 |
960 |
| T1 |
4449 |
2043 |
0 |
1 |
| T2 |
3859 |
0 |
0 |
1 |
| T3 |
1725 |
0 |
0 |
1 |
| T4 |
17135 |
0 |
0 |
1 |
| T5 |
794438 |
0 |
0 |
1 |
| T7 |
0 |
732 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
1 |
| T11 |
6189 |
0 |
0 |
1 |
| T20 |
0 |
4384 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
1 |
| T31 |
0 |
2230 |
0 |
0 |
| T32 |
0 |
912 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
1 |
| T34 |
0 |
1618 |
0 |
0 |
| T39 |
0 |
1128 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
1 |
| T70 |
0 |
1089 |
0 |
0 |
| T71 |
0 |
1319 |
0 |
0 |
| T72 |
0 |
1514 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
235601321 |
163923 |
0 |
0 |
| T1 |
4449 |
2043 |
0 |
0 |
| T2 |
3859 |
0 |
0 |
0 |
| T3 |
1725 |
0 |
0 |
0 |
| T4 |
17135 |
0 |
0 |
0 |
| T5 |
794438 |
0 |
0 |
0 |
| T7 |
0 |
732 |
0 |
0 |
| T10 |
2304 |
0 |
0 |
0 |
| T11 |
6189 |
0 |
0 |
0 |
| T20 |
0 |
4384 |
0 |
0 |
| T28 |
2715 |
0 |
0 |
0 |
| T31 |
0 |
2230 |
0 |
0 |
| T32 |
0 |
912 |
0 |
0 |
| T33 |
1180 |
0 |
0 |
0 |
| T34 |
0 |
1618 |
0 |
0 |
| T39 |
0 |
1128 |
0 |
0 |
| T41 |
1288 |
0 |
0 |
0 |
| T70 |
0 |
1089 |
0 |
0 |
| T71 |
0 |
1319 |
0 |
0 |
| T72 |
0 |
1514 |
0 |
0 |