Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	690310	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5679762

1

T1

10

T2

25

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1670703	1			T1	46		T2	49		T3	1
values[0x0]	2171046	1			T1	5		T2	15		T3	5
values[0x1]	2528323	1			T1	7		T2	10		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	337802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6032270

1

T1

28

T2

39

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23672	1			T16	1		T9	1		T22	1
valid_sources[0x01]	24831	1			T2	20		T5	1		T32	11
valid_sources[0x02]	24975	1			T4	7		T67	2		T74	1
valid_sources[0x03]	24500	1			T22	2		T23	196		T35	1
valid_sources[0x04]	25004	1			T74	1		T75	1		T27	7
valid_sources[0x05]	24869	1			T5	1		T8	1		T27	4
valid_sources[0x06]	23847	1			T1	1		T5	2		T22	1
valid_sources[0x07]	25477	1			T1	1		T16	2		T22	1
valid_sources[0x08]	24667	1			T5	1		T8	1		T74	2
valid_sources[0x09]	26048	1			T9	2		T21	1		T29	1
valid_sources[0x0a]	24964	1			T1	2		T16	1		T9	2
valid_sources[0x0b]	26643	1			T1	1		T22	3		T66	1
valid_sources[0x0c]	25313	1			T16	1		T5	2		T74	1
valid_sources[0x0d]	24768	1			T22	1		T66	6		T21	1
valid_sources[0x0e]	24307	1			T5	1		T8	1		T76	2
valid_sources[0x0f]	24511	1			T8	2		T22	1		T68	2
valid_sources[0x10]	24129	1			T1	1		T74	1		T27	3
valid_sources[0x11]	25039	1			T8	2		T22	1		T44	6
valid_sources[0x12]	24793	1			T22	1		T66	1		T23	216
valid_sources[0x13]	24245	1			T74	1		T77	1		T92	6
valid_sources[0x14]	25531	1			T9	2		T27	1		T29	1
valid_sources[0x15]	24672	1			T5	2		T22	3		T21	2
valid_sources[0x16]	24145	1			T5	1		T22	1		T44	2
valid_sources[0x17]	24111	1			T67	2		T68	3		T27	3
valid_sources[0x18]	24374	1			T66	18		T21	1		T76	1
valid_sources[0x19]	24527	1			T22	1		T74	1		T76	1
valid_sources[0x1a]	23712	1			T16	1		T74	2		T27	7
valid_sources[0x1b]	24892	1			T21	1		T77	1		T92	1
valid_sources[0x1c]	26834	1			T16	4		T21	1		T74	1
valid_sources[0x1d]	25255	1			T1	1		T22	1		T74	1
valid_sources[0x1e]	26499	1			T22	1		T23	217		T59	2
valid_sources[0x1f]	24952	1			T1	1		T8	2		T22	1
valid_sources[0x20]	24026	1			T23	258		T35	5		T78	1
valid_sources[0x21]	26068	1			T1	2		T32	9		T74	3
valid_sources[0x22]	25876	1			T16	1		T5	1		T22	1
valid_sources[0x23]	27264	1			T75	1		T27	2		T23	201
valid_sources[0x24]	23682	1			T1	1		T8	1		T27	1
valid_sources[0x25]	23689	1			T8	1		T23	300		T35	2
valid_sources[0x26]	25054	1			T9	1		T27	1		T77	1
valid_sources[0x27]	24867	1			T22	1		T21	1		T74	3
valid_sources[0x28]	24998	1			T16	6		T5	1		T74	3
valid_sources[0x29]	25526	1			T16	2		T8	1		T22	1
valid_sources[0x2a]	23843	1			T5	1		T22	2		T67	2
valid_sources[0x2b]	23570	1			T16	3		T22	1		T27	1
valid_sources[0x2c]	26072	1			T27	2		T29	1		T23	268
valid_sources[0x2d]	25376	1			T9	3		T21	2		T18	19
valid_sources[0x2e]	24758	1			T22	2		T68	4		T23	245
valid_sources[0x2f]	25173	1			T1	1		T76	1		T23	219
valid_sources[0x30]	24711	1			T1	1		T8	1		T22	1
valid_sources[0x31]	24061	1			T16	1		T22	1		T21	1
valid_sources[0x32]	24913	1			T8	1		T9	2		T27	1
valid_sources[0x33]	24435	1			T22	1		T27	3		T77	1
valid_sources[0x34]	24482	1			T1	2		T8	1		T9	2
valid_sources[0x35]	24577	1			T27	4		T29	1		T23	214
valid_sources[0x36]	25574	1			T9	1		T22	3		T27	4
valid_sources[0x37]	23998	1			T1	1		T16	1		T22	2
valid_sources[0x38]	23966	1			T2	3		T5	3		T18	10
valid_sources[0x39]	25304	1			T21	1		T75	1		T28	2
valid_sources[0x3a]	26549	1			T77	2		T28	2		T23	281
valid_sources[0x3b]	25827	1			T5	3		T9	1		T77	1
valid_sources[0x3c]	23293	1			T1	1		T8	1		T21	1
valid_sources[0x3d]	24655	1			T16	2		T5	1		T92	1
valid_sources[0x3e]	27355	1			T9	1		T27	4		T28	1
valid_sources[0x3f]	25186	1			T1	2		T16	2		T22	1
valid_sources[0x40]	24390	1			T1	1		T16	1		T5	1
valid_sources[0x41]	24567	1			T68	1		T23	268		T163	3
valid_sources[0x42]	24538	1			T16	2		T22	1		T74	1
valid_sources[0x43]	23901	1			T22	1		T66	7		T23	242
valid_sources[0x44]	25693	1			T5	1		T29	1		T23	238
valid_sources[0x45]	24983	1			T20	3		T5	1		T32	11
valid_sources[0x46]	25286	1			T1	1		T5	1		T28	3
valid_sources[0x47]	24350	1			T5	1		T9	1		T22	1
valid_sources[0x48]	25334	1			T1	2		T9	1		T21	1
valid_sources[0x49]	24518	1			T8	1		T67	7		T27	3
valid_sources[0x4a]	22966	1			T74	1		T27	4		T28	1
valid_sources[0x4b]	24690	1			T5	2		T67	1		T92	1
valid_sources[0x4c]	26180	1			T1	1		T16	1		T5	1
valid_sources[0x4d]	25352	1			T22	1		T21	2		T23	208
valid_sources[0x4e]	24570	1			T8	1		T44	5		T28	2
valid_sources[0x4f]	24507	1			T27	1		T92	1		T23	192
valid_sources[0x50]	24478	1			T8	1		T22	1		T28	1
valid_sources[0x51]	25830	1			T9	1		T22	1		T75	1
valid_sources[0x52]	23501	1			T1	1		T8	1		T74	1
valid_sources[0x53]	24968	1			T5	2		T9	1		T74	1
valid_sources[0x54]	24226	1			T1	1		T27	5		T41	1
valid_sources[0x55]	23955	1			T8	1		T22	1		T21	1
valid_sources[0x56]	25198	1			T1	1		T32	1		T23	277
valid_sources[0x57]	24611	1			T4	10		T66	1		T74	2
valid_sources[0x58]	24358	1			T21	2		T74	1		T27	1
valid_sources[0x59]	26785	1			T22	2		T66	3		T21	1
valid_sources[0x5a]	25578	1			T16	1		T22	1		T74	1
valid_sources[0x5b]	24855	1			T16	2		T22	1		T21	2
valid_sources[0x5c]	24276	1			T5	2		T74	1		T77	1
valid_sources[0x5d]	25071	1			T5	1		T22	3		T21	1
valid_sources[0x5e]	24762	1			T8	1		T22	1		T27	3
valid_sources[0x5f]	24677	1			T16	1		T5	1		T22	2
valid_sources[0x60]	23709	1			T27	1		T76	1		T77	1
valid_sources[0x61]	24621	1			T21	1		T75	1		T27	3
valid_sources[0x62]	24344	1			T8	1		T9	5		T22	1
valid_sources[0x63]	25100	1			T5	1		T92	1		T29	1
valid_sources[0x64]	24979	1			T16	3		T9	1		T22	1
valid_sources[0x65]	25257	1			T22	1		T74	1		T28	3
valid_sources[0x66]	25882	1			T5	2		T22	1		T21	1
valid_sources[0x67]	24667	1			T9	1		T67	6		T76	1
valid_sources[0x68]	26185	1			T21	2		T74	1		T28	1
valid_sources[0x69]	25260	1			T2	15		T16	1		T5	2
valid_sources[0x6a]	24882	1			T74	1		T77	1		T92	3
valid_sources[0x6b]	24406	1			T1	2		T75	1		T77	1
valid_sources[0x6c]	23411	1			T16	2		T41	1		T92	1
valid_sources[0x6d]	24845	1			T9	1		T22	1		T67	1
valid_sources[0x6e]	24525	1			T1	1		T22	1		T66	1
valid_sources[0x6f]	26161	1			T1	1		T22	1		T77	1
valid_sources[0x70]	25620	1			T9	1		T22	1		T67	5
valid_sources[0x71]	24385	1			T16	1		T21	1		T76	4
valid_sources[0x72]	25856	1			T21	1		T17	86		T76	2
valid_sources[0x73]	25790	1			T8	1		T74	1		T76	1
valid_sources[0x74]	25153	1			T9	1		T22	1		T74	2
valid_sources[0x75]	25314	1			T16	3		T22	1		T27	2
valid_sources[0x76]	23963	1			T32	1		T92	1		T23	217
valid_sources[0x77]	24648	1			T8	1		T9	1		T22	2
valid_sources[0x78]	25499	1			T1	1		T21	1		T67	5
valid_sources[0x79]	25479	1			T16	3		T22	1		T76	1
valid_sources[0x7a]	23822	1			T22	1		T21	1		T74	2
valid_sources[0x7b]	23510	1			T66	2		T27	7		T23	196
valid_sources[0x7c]	24878	1			T21	1		T29	1		T23	260
valid_sources[0x7d]	24476	1			T1	1		T8	1		T9	1
valid_sources[0x7e]	25049	1			T22	1		T23	225		T249	1
valid_sources[0x7f]	24237	1			T27	1		T28	1		T23	210
valid_sources[0x80]	24884	1			T16	1		T32	66		T22	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1429876

1

T1

5

T2

5

T4

1

values[0x0]

all_enables

biggest_size

2125799

1

T1

3

T2

11

T3

1

values[0x1]

all_enables

biggest_size

2124087

1

T1

2

T2

9

T3

2