Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2633	1			T2	1		T8	4		T32	3
non_zero_bins[1]	1958	1			T2	1		T9	4		T17	1
zero	9225	1			T1	2		T2	5		T4	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	519	1			T22	1		T69	1		T77	1
uni	3636	1			T2	2		T8	1		T32	2
gen	4377	1			T1	1		T2	2		T4	1
res	889	1			T2	1		T5	1		T8	2
ins	4395	1			T1	1		T2	2		T4	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9148

1

T1

2

T2

5

T4

2

mubi_true

4668

1

T2

2

T4

1

T16

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

14

1

T159

1

T296

1

T297

1

pass

13802

1

T1

2

T2

7

T4

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	112	1			T36	1		T164	1		T39	1
upd	non_zero_bins[0]	pass	mubi_true	113	1			T22	1		T69	1		T77	1
upd	non_zero_bins[1]	pass	mubi_false	85	1			T31	1		T157	2		T243	2
upd	non_zero_bins[1]	pass	mubi_true	109	1			T23	2		T42	1		T24	1
upd	zero	pass	mubi_false	42	1			T161	1		T157	1		T245	1
upd	zero	pass	mubi_true	58	1			T43	1		T24	3		T25	2
uni	zero	pass	mubi_false	2702	1			T2	2		T8	1		T32	2
uni	zero	pass	mubi_true	934	1			T66	1		T68	1		T75	1
gen	non_zero_bins[0]	pass	mubi_false	501	1			T8	3		T17	3		T68	1
gen	non_zero_bins[0]	pass	mubi_true	475	1			T32	1		T27	1		T19	3
gen	non_zero_bins[1]	pass	mubi_false	412	1			T2	1		T9	4		T18	4
gen	non_zero_bins[1]	pass	mubi_true	321	1			T26	1		T76	1		T31	1
gen	zero	fail	mubi_false	12	1			T159	1		T296	1		T297	1
gen	zero	pass	mubi_false	1922	1			T1	1		T2	1		T5	1
gen	zero	pass	mubi_true	734	1			T4	1		T16	2		T20	2
res	non_zero_bins[0]	pass	mubi_false	205	1			T9	2		T19	4		T23	2
res	non_zero_bins[0]	pass	mubi_true	169	1			T17	2		T74	1		T27	1
res	non_zero_bins[1]	pass	mubi_false	147	1			T26	1		T76	1		T28	2
res	non_zero_bins[1]	pass	mubi_true	158	1			T18	2		T23	1		T24	2
res	zero	fail	mubi_false	2	1			T201	1		T301	1		-	-
res	zero	pass	mubi_false	102	1			T5	1		T23	1		T158	1
res	zero	pass	mubi_true	106	1			T2	1		T8	2		T19	1
ins	non_zero_bins[0]	pass	mubi_false	529	1			T32	2		T74	1		T27	1
ins	non_zero_bins[0]	pass	mubi_true	529	1			T2	1		T8	1		T68	1
ins	non_zero_bins[1]	pass	mubi_false	356	1			T18	1		T23	3		T160	2
ins	non_zero_bins[1]	pass	mubi_true	370	1			T17	1		T26	1		T23	4
ins	zero	pass	mubi_false	2019	1			T1	1		T2	1		T4	2
ins	zero	pass	mubi_true	592	1			T16	1		T20	1		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded