Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T4,T33,T29
1	1	Covered	T2,T4,T16

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T16,T5,T19
1	1	Covered	T5,T8,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T20,T21
1	0	Covered	T1,T4,T5

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T20,T21
1	Covered	T1,T4,T5

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T16,T20,T21
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T1,T4,T5

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T5,T8,T9
AutoCaptGenCnt	143	Covered	T5,T8,T9
AutoCaptReseedCnt	141	Covered	T5,T8,T9
AutoDispatch	125	Covered	T5,T8,T9
AutoFirstAckWait	119	Covered	T5,T8,T9
AutoLoadIns	69	Covered	T5,T8,T9
AutoSendGenCmd	150	Covered	T5,T8,T9
AutoSendReseedCmd	162	Covered	T5,T8,T9
BootDone	98	Covered	T2,T4,T22
BootGenAckWait	90	Covered	T2,T4,T22
BootInsAckWait	80	Covered	T2,T4,T16
BootLoadGen	85	Covered	T2,T4,T22
BootLoadIns	65	Covered	T2,T4,T16
BootLoadUni	102	Covered	T2,T22,T67
BootPulse	94	Covered	T2,T4,T22
BootUniAckWait	107	Covered	T2,T22,T67
Error	188	Covered	T1,T4,T5
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T16,T20,T21
SWPortMode	74	Covered	T1,T2,T16

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T5,T8,T9
AutoAckWait->Error	188	Covered	T169
AutoAckWait->Idle	211	Covered	T19,T59,T60
AutoAckWait->RejectCsrngEntropy	188	Covered	T67,T29,T158
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T5,T8,T9
AutoCaptGenCnt->Error	188	Covered	T117,T107
AutoCaptGenCnt->Idle	211	Covered	T170,T150,T129
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T171,T172,T173
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T5,T8,T9
AutoCaptReseedCnt->Error	188	Covered	T174,T175,T176
AutoCaptReseedCnt->Idle	211	Covered	T65,T177,T178
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T179,T180,T181
AutoDispatch->AutoCaptGenCnt	143	Covered	T5,T8,T9
AutoDispatch->AutoCaptReseedCnt	141	Covered	T5,T8,T9
AutoDispatch->Error	188	Covered	T50,T182,T183
AutoDispatch->Idle	138	Covered	T8,T9,T17
AutoDispatch->RejectCsrngEntropy	188	Covered	T184,T156,T185
AutoFirstAckWait->AutoDispatch	125	Covered	T5,T8,T9
AutoFirstAckWait->Error	188	Covered	T186
AutoFirstAckWait->Idle	211	Covered	T108,T187,T188
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T53,T55,T189
AutoLoadIns->AutoFirstAckWait	119	Covered	T5,T8,T9
AutoLoadIns->Error	188	Covered	T6,T52,T190
AutoLoadIns->Idle	211	Covered	T5,T158,T37
AutoLoadIns->RejectCsrngEntropy	188	Covered	T191,T192,T193
AutoSendGenCmd->AutoAckWait	156	Covered	T5,T8,T9
AutoSendGenCmd->Error	188	Covered	T194,T136,T195
AutoSendGenCmd->Idle	211	Covered	T60,T116,T134
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T73,T196,T197
AutoSendReseedCmd->AutoAckWait	168	Covered	T8,T9,T17
AutoSendReseedCmd->Error	188	Covered	T5,T198
AutoSendReseedCmd->Idle	211	Covered	T91,T199,T200
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T165,T201,T202
BootDone->BootLoadUni	102	Covered	T2,T22,T67
BootDone->Error	188	Covered	T203,T204,T205
BootDone->Idle	211	Covered	T206,T207,T208
BootDone->RejectCsrngEntropy	188	Covered	T21,T209,T210
BootGenAckWait->BootPulse	94	Covered	T2,T4,T22
BootGenAckWait->Error	188	Covered	T137,T211
BootGenAckWait->Idle	211	Covered	T118,T123,T49
BootGenAckWait->RejectCsrngEntropy	188	Covered	T81,T212,T213
BootInsAckWait->BootLoadGen	85	Covered	T2,T4,T22
BootInsAckWait->Error	188	Covered	T4,T51,T214
BootInsAckWait->Idle	211	Covered	T4,T115,T71
BootInsAckWait->RejectCsrngEntropy	188	Covered	T16,T20,T162
BootLoadGen->BootGenAckWait	90	Covered	T2,T4,T22
BootLoadGen->Error	188	Covered	T215,T131
BootLoadGen->Idle	211	Covered	T143,T125,T216
BootLoadGen->RejectCsrngEntropy	188	Covered	T35,T72,T217
BootLoadIns->BootInsAckWait	80	Covered	T2,T4,T16
BootLoadIns->Error	188	Covered	T121,T122,T218
BootLoadIns->Idle	211	Covered	T33,T119,T120
BootLoadIns->RejectCsrngEntropy	188	Covered	T41,T92,T93
BootLoadUni->BootUniAckWait	107	Covered	T2,T22,T67
BootLoadUni->Error	188	Covered	T219
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T220,T221,T222
BootPulse->BootDone	98	Covered	T2,T4,T22
BootPulse->Error	188	Covered	T118,T146,T223
BootPulse->Idle	211	Covered	T79,T224,T225
BootPulse->RejectCsrngEntropy	188	Covered	T78,T37,T226
BootUniAckWait->Error	188	Covered	T49,T227,T127
BootUniAckWait->Idle	112	Covered	T2,T22,T67
BootUniAckWait->RejectCsrngEntropy	188	Covered	T167,T228,T229
Idle->AutoLoadIns	69	Covered	T5,T8,T9
Idle->BootLoadIns	65	Covered	T2,T4,T16
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T16,T21,T92
Idle->SWPortMode	74	Covered	T1,T2,T16
RejectCsrngEntropy->Error	188	Covered	T230,T231,T232
RejectCsrngEntropy->Idle	211	Covered	T16,T20,T21
SWPortMode->Error	188	Covered	T1,T44,T13
SWPortMode->Idle	211	Covered	T16,T20,T21
SWPortMode->RejectCsrngEntropy	188	Covered	T20,T67,T41

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T16
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T22
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T22
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T22
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T22
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T22,T67
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T21,T67
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T22,T67
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T22,T68
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T22,T67
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T8,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T8,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T8,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T9,T17
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T5,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T5,T8,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T5,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T5,T8,T9
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T17
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T8,T9
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T20,T21
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T45,T38,T70

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T16,T20,T21
0	-	-	1	Covered	T4,T16,T20
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	232864084	84478	0	0
FpvSecCmErrorStEscalate_A	232864084	84610	0	0
u_state_regs_A	232833013	232731725	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	84478	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	542	0	0
T44	0	1143	0	0
T45	498	192	0	0
T70	0	577	0	0
T71	0	1060	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	84610	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	543	0	0
T44	0	1144	0	0
T45	498	193	0	0
T70	0	578	0	0
T71	0	1061	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232833013	232731725	0	0
T1	558	401	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	849	729	0	0
T5	701	521	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	333	194	0	0