Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T16
DataWait	75	Covered	T1,T2,T16
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T112,T113,T114
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T16
DataWait->AckPls	80	Covered	T1,T2,T16
DataWait->Disabled	107	Covered	T115,T60,T116
DataWait->Error	99	Covered	T7,T117,T118
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T1,T2,T16
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T1,T2,T16
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T1,T2,T16
DataWait	-	-	-	0	Covered	T2,T16,T20
AckPls	-	-	-	-	Covered	T1,T2,T16
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1630048588	606296	0	0
FpvSecCmErrorStEscalate_A	1630048588	607220	0	0
u_state_regs_A	1630017517	1629308501	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630048588	606296	0	0
T1	4690	1826	0	0
T2	13853	0	0	0
T3	6853	0	0	0
T4	6790	3940	0	0
T5	6517	2470	0	0
T6	0	3114	0	0
T8	17430	0	0	0
T13	0	7056	0	0
T16	16793	0	0	0
T20	11403	0	0	0
T32	10801	0	0	0
T38	0	4144	0	0
T44	0	7951	0	0
T45	3486	1694	0	0
T70	0	4389	0	0
T71	0	7770	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630048588	607220	0	0
T1	4690	1833	0	0
T2	13853	0	0	0
T3	6853	0	0	0
T4	6790	3947	0	0
T5	6517	2477	0	0
T6	0	3121	0	0
T8	17430	0	0	0
T13	0	7063	0	0
T16	16793	0	0	0
T20	11403	0	0	0
T32	10801	0	0	0
T38	0	4151	0	0
T44	0	7958	0	0
T45	3486	1701	0	0
T70	0	4396	0	0
T71	0	7777	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1630017517	1629308501	0	0
T1	4578	3479	0	0
T2	13853	13384	0	0
T3	6853	6265	0	0
T4	6669	5829	0	0
T5	6287	5027	0	0
T8	17430	16940	0	0
T16	16793	16366	0	0
T20	11403	10934	0	0
T32	10801	10318	0	0
T45	3321	2348	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T28,T29
DataWait	75	Covered	T18,T28,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T28,T29
DataWait->AckPls	80	Covered	T18,T28,T29
DataWait->Disabled	107	Covered	T124,T125
DataWait->Error	99	Covered	T126,T127,T128
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T18,T28,T29
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T18,T28,T29
Idle	-	1	0	-	Covered	T18,T28,T29
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T18,T28,T29
DataWait	-	-	-	0	Covered	T18,T28,T29
AckPls	-	-	-	-	Covered	T18,T28,T29
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	86928	0	0
FpvSecCmErrorStEscalate_A	232864084	87060	0	0
u_state_regs_A	232864084	232762796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	86928	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1143	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87060	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1144	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T21,T18
DataWait	75	Covered	T9,T21,T18
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T21,T18
DataWait->AckPls	80	Covered	T9,T21,T18
DataWait->Disabled	107	Covered	T129
DataWait->Error	99	Covered	T130,T131
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T9,T21,T18
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T9,T21,T18
Idle	-	1	0	-	Covered	T9,T21,T18
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T9,T21,T18
DataWait	-	-	-	0	Covered	T9,T21,T18
AckPls	-	-	-	-	Covered	T9,T21,T18
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	86928	0	0
FpvSecCmErrorStEscalate_A	232864084	87060	0	0
u_state_regs_A	232864084	232762796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	86928	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1143	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87060	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1144	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T30,T31
DataWait	75	Covered	T28,T30,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T30,T31
DataWait->AckPls	80	Covered	T28,T30,T31
DataWait->Disabled	107	Covered	T132,T133,T134
DataWait->Error	99	Covered	T135,T136,T137
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T28,T30,T31
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T28,T30,T31
Idle	-	1	0	-	Covered	T28,T30,T31
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T28,T30,T31
DataWait	-	-	-	0	Covered	T28,T30,T31
AckPls	-	-	-	-	Covered	T28,T30,T31
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	86928	0	0
FpvSecCmErrorStEscalate_A	232864084	87060	0	0
u_state_regs_A	232864084	232762796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	86928	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1143	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87060	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1144	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T16
DataWait	75	Covered	T1,T2,T16
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T16
DataWait->AckPls	80	Covered	T1,T2,T16
DataWait->Disabled	107	Covered	T116,T138
DataWait->Error	99	Covered	T139,T50,T140
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T123,T141,T142
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T1,T2,T16
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T45,T38,T70

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T1,T2,T16
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T1,T2,T16
DataWait	-	-	-	0	Covered	T2,T16,T5
AckPls	-	-	-	-	Covered	T1,T2,T16
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	84728	0	0
FpvSecCmErrorStEscalate_A	232864084	84860	0	0
u_state_regs_A	232833013	232731725	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	84728	0	0
T1	670	218	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	520	0	0
T5	931	310	0	0
T6	0	402	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1093	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	84860	0	0
T1	670	219	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	521	0	0
T5	931	311	0	0
T6	0	403	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1094	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232833013	232731725	0	0
T1	558	401	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	849	729	0	0
T5	701	521	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	333	194	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T26,T27
DataWait	75	Covered	T18,T26,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T114
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T26,T27
DataWait->AckPls	80	Covered	T18,T26,T27
DataWait->Disabled	107	Covered	T143,T144,T145
DataWait->Error	99	Covered	T117,T146,T147
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T18,T26,T27
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T18,T26,T27
Idle	-	1	0	-	Covered	T18,T26,T27
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T18,T26,T27
DataWait	-	-	-	0	Covered	T18,T26,T27
AckPls	-	-	-	-	Covered	T18,T26,T27
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	86928	0	0
FpvSecCmErrorStEscalate_A	232864084	87060	0	0
u_state_regs_A	232864084	232762796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	86928	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1143	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87060	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1144	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T18,T27
DataWait	75	Covered	T20,T18,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T113,T148
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T18,T27
DataWait->AckPls	80	Covered	T20,T18,T27
DataWait->Disabled	107	Covered	T115,T149,T150
DataWait->Error	99	Covered	T7,T118,T151
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T20,T18,T27
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T20,T18,T27
Idle	-	1	0	-	Covered	T20,T18,T27
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T20,T18,T27
DataWait	-	-	-	0	Covered	T20,T18,T27
AckPls	-	-	-	-	Covered	T20,T18,T27
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	86928	0	0
FpvSecCmErrorStEscalate_A	232864084	87060	0	0
u_state_regs_A	232864084	232762796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	86928	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1143	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87060	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1144	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T16,T20

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T18,T19
DataWait	75	Covered	T21,T18,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T1,T4,T5
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T112
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T18,T19
DataWait->AckPls	80	Covered	T21,T18,T19
DataWait->Disabled	107	Covered	T60,T85,T152
DataWait->Error	99	Covered	T71,T153,T49
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T33,T119,T120
EndPointClear->Error	99	Covered	T121,T122,T123
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T21,T18,T19
Idle->Disabled	107	Covered	T4,T16,T20
Idle->Error	99	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T21,T18,T19
Idle	-	1	0	-	Covered	T21,T18,T19
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T21,T18,T19
DataWait	-	-	-	0	Covered	T18,T19,T28
AckPls	-	-	-	-	Covered	T21,T18,T19
Error	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T4,T16,T20
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	232864084	86928	0	0
FpvSecCmErrorStEscalate_A	232864084	87060	0	0
u_state_regs_A	232864084	232762796	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	86928	0	0
T1	670	268	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	570	0	0
T5	931	360	0	0
T6	0	452	0	0
T8	2490	0	0	0
T13	0	1008	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	592	0	0
T44	0	1143	0	0
T45	498	242	0	0
T70	0	627	0	0
T71	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87060	0	0
T1	670	269	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	571	0	0
T5	931	361	0	0
T6	0	453	0	0
T8	2490	0	0	0
T13	0	1009	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	593	0	0
T44	0	1144	0	0
T45	498	243	0	0
T70	0	628	0	0
T71	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0