Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T16,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T103,T106
1	1	0	Not Covered
1	1	1	Covered	T4,T16,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T54,T100,T101
1	0	1	Covered	T4,T16,T5
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T16,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	465387276	1110722	0	0
DepthKnown_A	465728168	465525592	0	0
RvalidKnown_A	465728168	465525592	0	0
WreadyKnown_A	465728168	465525592	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	465728168	1179223	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465387276	1110722	0	0
T5	286	63	0	0
T8	4980	2017	0	0
T9	14276	10732	0	0
T16	4798	67	0	0
T17	0	10519	0	0
T18	0	5183	0	0
T19	0	4451	0	0
T20	3258	0	0	0
T22	2584	0	0	0
T28	0	1929	0	0
T32	3086	0	0	0
T44	868	0	0	0
T45	154	0	0	0
T66	2976	0	0	0
T67	0	604	0	0
T92	0	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465728168	465525592	0	0
T1	1340	1026	0	0
T2	3958	3824	0	0
T3	1958	1790	0	0
T4	1940	1700	0	0
T5	1862	1502	0	0
T8	4980	4840	0	0
T16	4798	4676	0	0
T20	3258	3124	0	0
T32	3086	2948	0	0
T45	996	718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465728168	465525592	0	0
T1	1340	1026	0	0
T2	3958	3824	0	0
T3	1958	1790	0	0
T4	1940	1700	0	0
T5	1862	1502	0	0
T8	4980	4840	0	0
T16	4798	4676	0	0
T20	3258	3124	0	0
T32	3086	2948	0	0
T45	996	718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465728168	465525592	0	0
T1	1340	1026	0	0
T2	3958	3824	0	0
T3	1958	1790	0	0
T4	1940	1700	0	0
T5	1862	1502	0	0
T8	4980	4840	0	0
T16	4798	4676	0	0
T20	3258	3124	0	0
T32	3086	2948	0	0
T45	996	718	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	465728168	1179223	0	0
T4	1940	222	0	0
T5	1862	849	0	0
T8	4980	2017	0	0
T9	14276	10732	0	0
T16	4798	67	0	0
T17	0	10519	0	0
T18	0	5183	0	0
T19	0	4451	0	0
T20	3258	0	0	0
T22	2584	0	0	0
T32	3086	0	0	0
T44	4434	0	0	0
T45	996	259	0	0
T67	0	604	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T107,T108
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T16,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T106
1	1	0	Not Covered
1	1	1	Covered	T4,T16,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T54,T109,T110
1	0	1	Covered	T4,T16,T5
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T16,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	232693638	549746	0	0
DepthKnown_A	232864084	232762796	0	0
RvalidKnown_A	232864084	232762796	0	0
WreadyKnown_A	232864084	232762796	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	232864084	583852	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232693638	549746	0	0
T5	143	19	0	0
T8	2490	959	0	0
T9	7138	5356	0	0
T16	2399	29	0	0
T17	0	5226	0	0
T18	0	2585	0	0
T19	0	2173	0	0
T20	1629	0	0	0
T22	1292	0	0	0
T28	0	952	0	0
T32	1543	0	0	0
T44	434	0	0	0
T45	77	0	0	0
T66	1488	0	0	0
T67	0	305	0	0
T92	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	583852	0	0
T4	970	112	0	0
T5	931	409	0	0
T8	2490	959	0	0
T9	7138	5356	0	0
T16	2399	29	0	0
T17	0	5226	0	0
T18	0	2585	0	0
T19	0	2173	0	0
T20	1629	0	0	0
T22	1292	0	0	0
T32	1543	0	0	0
T44	2217	0	0	0
T45	498	132	0	0
T67	0	305	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T16,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T103
1	1	0	Not Covered
1	1	1	Covered	T4,T16,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T100,T101,T111
1	0	1	Covered	T4,T16,T5
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T16,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	232693638	560976	0	0
DepthKnown_A	232864084	232762796	0	0
RvalidKnown_A	232864084	232762796	0	0
WreadyKnown_A	232864084	232762796	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	232864084	595371	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232693638	560976	0	0
T5	143	44	0	0
T8	2490	1058	0	0
T9	7138	5376	0	0
T16	2399	38	0	0
T17	0	5293	0	0
T18	0	2598	0	0
T19	0	2278	0	0
T20	1629	0	0	0
T22	1292	0	0	0
T28	0	977	0	0
T32	1543	0	0	0
T44	434	0	0	0
T45	77	0	0	0
T66	1488	0	0	0
T67	0	299	0	0
T92	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	595371	0	0
T4	970	110	0	0
T5	931	440	0	0
T8	2490	1058	0	0
T9	7138	5376	0	0
T16	2399	38	0	0
T17	0	5293	0	0
T18	0	2598	0	0
T19	0	2278	0	0
T20	1629	0	0	0
T22	1292	0	0	0
T32	1543	0	0	0
T44	2217	0	0	0
T45	498	127	0	0
T67	0	299	0	0