Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
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Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
58.33 58.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_sw_cmd_sts_cg 58.33 1 100 1 64 64




Group Instance : edn_sw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
58.33 1 100 1 64 64




Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 5 7 58.33


Variables for Group Instance edn_sw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_cmd_ack_cg 2 0 2 100.00 100 1 1 0
cp_cmd_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_reg_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_sts_cg 6 5 1 16.67 100 1 1 0


Summary for Variable cp_cmd_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 25089 1 T2 17 T3 25 T4 42
ack 20433 1 T2 5 T3 9 T4 42



Summary for Variable cp_cmd_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 24281 1 T2 17 T3 24 T4 40
ready 21241 1 T2 5 T3 10 T4 44



Summary for Variable cp_cmd_reg_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_reg_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 481 1 T2 1 T10 1 T15 1
ready 45041 1 T2 21 T3 34 T4 84



Summary for Variable cp_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 5 1 16.67


Automatically Generated Bins for cp_cmd_sts_cg

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[CMD_STS_INVALID_ACMD] 0 1 1
auto[CMD_STS_INVALID_GEN_CMD] 0 1 1
auto[CMD_STS_INVALID_CMD_SEQ] 0 1 1
auto[CMD_STS_RESEED_CNT_EXCEEDED] 0 1 1
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 45522 1 T2 22 T3 34 T4 84

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