Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	614035	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4875709

1

T1

53

T2

75

T3

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1452165	1			T1	31		T2	36		T3	70
values[0x0]	1864557	1			T1	24		T2	35		T3	15
values[0x1]	2173022	1			T1	33		T2	39		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	304359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5185385

1

T1

67

T2

83

T3

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21291	1			T4	1		T10	2		T53	34
valid_sources[0x01]	20378	1			T4	8		T24	1		T20	282
valid_sources[0x02]	19296	1			T9	1		T54	1		T20	339
valid_sources[0x03]	22611	1			T4	10		T19	1		T53	2
valid_sources[0x04]	20882	1			T2	3		T9	2		T4	13
valid_sources[0x05]	20366	1			T20	273		T21	335		T38	1
valid_sources[0x06]	19969	1			T24	1		T20	349		T34	1
valid_sources[0x07]	20306	1			T4	5		T20	374		T70	2
valid_sources[0x08]	21060	1			T2	1		T4	4		T23	7
valid_sources[0x09]	21585	1			T2	3		T4	5		T5	2
valid_sources[0x0a]	21722	1			T29	10		T20	331		T21	344
valid_sources[0x0b]	21636	1			T2	1		T9	2		T29	1
valid_sources[0x0c]	22459	1			T4	1		T20	292		T34	1
valid_sources[0x0d]	22896	1			T9	1		T4	6		T29	5
valid_sources[0x0e]	20712	1			T4	4		T20	315		T70	1
valid_sources[0x0f]	21600	1			T5	1		T7	1		T20	320
valid_sources[0x10]	20524	1			T2	1		T5	1		T19	1
valid_sources[0x11]	22318	1			T2	2		T4	4		T45	22
valid_sources[0x12]	21033	1			T4	1		T20	354		T70	1
valid_sources[0x13]	21572	1			T2	1		T5	1		T17	16
valid_sources[0x14]	20063	1			T5	3		T19	1		T7	2
valid_sources[0x15]	22003	1			T5	1		T15	1		T20	337
valid_sources[0x16]	22033	1			T2	1		T9	1		T24	2
valid_sources[0x17]	21238	1			T5	3		T24	1		T20	319
valid_sources[0x18]	21116	1			T2	1		T4	16		T24	1
valid_sources[0x19]	21352	1			T4	7		T20	315		T37	1
valid_sources[0x1a]	21533	1			T4	1		T7	1		T20	389
valid_sources[0x1b]	20619	1			T20	327		T21	301		T22	307
valid_sources[0x1c]	20976	1			T4	8		T54	2		T29	2
valid_sources[0x1d]	21905	1			T5	1		T19	1		T20	323
valid_sources[0x1e]	21075	1			T10	1		T54	2		T20	355
valid_sources[0x1f]	19637	1			T2	1		T4	6		T5	1
valid_sources[0x20]	19918	1			T4	3		T5	3		T24	1
valid_sources[0x21]	20841	1			T4	6		T17	8		T20	350
valid_sources[0x22]	22383	1			T2	1		T9	2		T24	1
valid_sources[0x23]	21378	1			T4	2		T7	1		T24	1
valid_sources[0x24]	21086	1			T53	1		T24	1		T20	302
valid_sources[0x25]	20639	1			T2	2		T9	2		T4	3
valid_sources[0x26]	20750	1			T2	2		T4	8		T5	2
valid_sources[0x27]	21765	1			T4	4		T5	2		T54	2
valid_sources[0x28]	19761	1			T4	5		T7	2		T29	11
valid_sources[0x29]	20649	1			T9	1		T4	5		T17	12
valid_sources[0x2a]	20679	1			T29	5		T20	316		T70	1
valid_sources[0x2b]	21154	1			T10	2		T54	1		T29	1
valid_sources[0x2c]	21281	1			T2	1		T9	1		T4	1
valid_sources[0x2d]	22472	1			T4	4		T24	1		T20	331
valid_sources[0x2e]	21666	1			T4	3		T5	1		T20	330
valid_sources[0x2f]	20995	1			T24	1		T20	343		T70	2
valid_sources[0x30]	23459	1			T4	4		T15	3		T20	416
valid_sources[0x31]	21044	1			T4	5		T5	1		T10	2
valid_sources[0x32]	20936	1			T10	3		T24	3		T20	347
valid_sources[0x33]	20629	1			T9	2		T4	8		T15	4
valid_sources[0x34]	21231	1			T7	3		T20	408		T25	1
valid_sources[0x35]	20283	1			T2	1		T7	2		T17	8
valid_sources[0x36]	22689	1			T4	1		T16	8		T54	1
valid_sources[0x37]	21478	1			T2	1		T9	1		T4	2
valid_sources[0x38]	20703	1			T4	4		T29	2		T20	337
valid_sources[0x39]	20258	1			T4	23		T20	326		T70	1
valid_sources[0x3a]	21987	1			T9	1		T4	7		T19	1
valid_sources[0x3b]	21053	1			T2	1		T4	2		T5	1
valid_sources[0x3c]	21065	1			T54	1		T29	1		T20	339
valid_sources[0x3d]	20732	1			T4	2		T10	3		T55	73
valid_sources[0x3e]	22247	1			T2	2		T10	1		T15	23
valid_sources[0x3f]	20882	1			T20	327		T37	2		T21	323
valid_sources[0x40]	22514	1			T9	1		T6	72		T10	2
valid_sources[0x41]	20844	1			T10	3		T24	3		T20	270
valid_sources[0x42]	22264	1			T2	2		T4	4		T5	3
valid_sources[0x43]	21683	1			T2	1		T44	250		T10	1
valid_sources[0x44]	23720	1			T4	1		T5	1		T20	320
valid_sources[0x45]	21466	1			T2	1		T19	2		T7	1
valid_sources[0x46]	19240	1			T9	1		T20	319		T21	367
valid_sources[0x47]	21110	1			T1	1		T9	2		T20	287
valid_sources[0x48]	19643	1			T10	2		T20	340		T70	1
valid_sources[0x49]	21869	1			T4	3		T20	271		T70	1
valid_sources[0x4a]	21405	1			T4	1		T10	1		T53	1
valid_sources[0x4b]	21538	1			T7	1		T24	1		T20	321
valid_sources[0x4c]	20332	1			T2	1		T24	1		T20	316
valid_sources[0x4d]	22246	1			T10	2		T53	2		T20	358
valid_sources[0x4e]	20973	1			T2	2		T4	2		T5	1
valid_sources[0x4f]	20889	1			T9	2		T4	17		T10	6
valid_sources[0x50]	22212	1			T2	1		T20	392		T71	3
valid_sources[0x51]	23086	1			T4	1		T10	3		T24	1
valid_sources[0x52]	21520	1			T5	2		T20	362		T70	1
valid_sources[0x53]	21796	1			T9	2		T4	13		T5	2
valid_sources[0x54]	22409	1			T1	4		T5	1		T20	358
valid_sources[0x55]	23561	1			T1	1		T2	2		T4	9
valid_sources[0x56]	22076	1			T4	2		T20	287		T34	1
valid_sources[0x57]	21406	1			T9	2		T4	5		T15	32
valid_sources[0x58]	20786	1			T9	1		T19	1		T24	1
valid_sources[0x59]	20464	1			T9	1		T4	4		T5	1
valid_sources[0x5a]	21423	1			T4	4		T24	1		T29	1
valid_sources[0x5b]	20857	1			T20	394		T34	1		T21	373
valid_sources[0x5c]	21040	1			T1	2		T4	14		T5	1
valid_sources[0x5d]	20306	1			T4	1		T16	6		T7	1
valid_sources[0x5e]	21725	1			T4	3		T5	1		T53	1
valid_sources[0x5f]	23049	1			T10	2		T15	5		T20	345
valid_sources[0x60]	22269	1			T9	1		T4	3		T5	1
valid_sources[0x61]	21721	1			T4	2		T19	2		T20	287
valid_sources[0x62]	20849	1			T1	1		T7	1		T20	347
valid_sources[0x63]	21042	1			T4	3		T7	1		T20	378
valid_sources[0x64]	21696	1			T5	1		T10	2		T7	1
valid_sources[0x65]	20888	1			T9	1		T24	1		T20	318
valid_sources[0x66]	22066	1			T2	1		T5	2		T7	1
valid_sources[0x67]	20071	1			T4	7		T7	2		T20	296
valid_sources[0x68]	22243	1			T4	1		T24	1		T29	1
valid_sources[0x69]	20808	1			T1	37		T4	14		T5	1
valid_sources[0x6a]	21664	1			T2	2		T29	7		T20	364
valid_sources[0x6b]	19969	1			T9	2		T4	1		T20	295
valid_sources[0x6c]	20159	1			T2	6		T7	2		T20	264
valid_sources[0x6d]	21244	1			T5	4		T10	2		T19	2
valid_sources[0x6e]	20472	1			T9	3		T29	4		T20	277
valid_sources[0x6f]	20971	1			T5	1		T20	348		T70	1
valid_sources[0x70]	22184	1			T4	1		T5	1		T20	379
valid_sources[0x71]	21823	1			T4	11		T17	31		T24	1
valid_sources[0x72]	21732	1			T1	1		T10	1		T20	330
valid_sources[0x73]	20521	1			T5	1		T13	3		T7	1
valid_sources[0x74]	19899	1			T4	11		T5	1		T53	2
valid_sources[0x75]	22212	1			T9	1		T7	1		T29	1
valid_sources[0x76]	23708	1			T9	1		T5	1		T10	2
valid_sources[0x77]	20145	1			T7	2		T20	331		T34	2
valid_sources[0x78]	21467	1			T53	1		T20	389		T70	1
valid_sources[0x79]	22175	1			T2	1		T9	1		T4	1
valid_sources[0x7a]	22903	1			T2	1		T9	3		T4	8
valid_sources[0x7b]	21076	1			T9	1		T5	1		T29	1
valid_sources[0x7c]	21841	1			T9	1		T4	1		T5	2
valid_sources[0x7d]	20802	1			T29	5		T20	326		T25	7
valid_sources[0x7e]	21580	1			T10	2		T54	1		T20	355
valid_sources[0x7f]	20198	1			T1	2		T9	3		T4	4
valid_sources[0x80]	23029	1			T5	2		T7	1		T29	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1229443

1

T1

13

T2

5

T3

5

values[0x0]

all_enables

biggest_size

1824379

1

T1

16

T2

34

T3

14

values[0x1]

all_enables

biggest_size

1821887

1

T1

24

T2

36

T3

19