Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2635 1 T2 1 T3 1 T4 5
non_zero_bins[1] 1763 1 T2 6 T3 2 T4 3
zero 8932 1 T1 5 T2 1 T3 5



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 498 1 T4 1 T20 22 T21 14
uni 3497 1 T2 1 T3 3 T4 7
gen 4253 1 T1 3 T2 4 T3 2
res 830 1 T2 2 T4 1 T10 2
ins 4252 1 T1 2 T2 1 T3 3



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 8755 1 T1 2 T2 2 T3 5
mubi_true 4575 1 T1 3 T2 6 T3 3



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 25 1 T70 1 T69 1 T75 1
pass 13305 1 T1 5 T2 8 T3 8



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 126 1 T4 1 T20 6 T21 4
upd non_zero_bins[0] pass mubi_true 116 1 T20 5 T21 3 T22 2
upd non_zero_bins[1] pass mubi_false 78 1 T20 2 T21 1 T22 1
upd non_zero_bins[1] pass mubi_true 78 1 T20 4 T21 1 T96 1
upd zero pass mubi_false 45 1 T20 3 T21 4 T22 1
upd zero pass mubi_true 55 1 T20 2 T21 1 T22 2
uni zero pass mubi_false 2573 1 T2 1 T3 3 T4 5
uni zero pass mubi_true 924 1 T4 2 T44 1 T55 1
gen non_zero_bins[0] pass mubi_false 533 1 T3 1 T4 1 T44 1
gen non_zero_bins[0] pass mubi_true 518 1 T2 1 T10 7 T55 1
gen non_zero_bins[1] pass mubi_false 278 1 T20 8 T21 4 T22 3
gen non_zero_bins[1] pass mubi_true 354 1 T2 3 T4 2 T16 1
gen zero fail mubi_false 18 1 T70 1 T75 1 T267 1
gen zero pass mubi_false 1850 1 T1 1 T4 3 T5 1
gen zero pass mubi_true 702 1 T1 2 T3 1 T9 2
res non_zero_bins[0] pass mubi_false 181 1 T4 1 T20 8 T22 3
res non_zero_bins[0] pass mubi_true 165 1 T10 2 T20 3 T21 5
res non_zero_bins[1] pass mubi_false 127 1 T16 2 T20 1 T25 4
res non_zero_bins[1] pass mubi_true 149 1 T2 2 T15 1 T17 2
res zero fail mubi_false 7 1 T69 1 T172 1 T268 1
res zero pass mubi_false 115 1 T20 1 T21 2 T22 1
res zero pass mubi_true 86 1 T20 1 T21 1 T269 2
ins non_zero_bins[0] pass mubi_false 520 1 T4 1 T44 1 T29 1
ins non_zero_bins[0] pass mubi_true 476 1 T4 1 T10 1 T15 2
ins non_zero_bins[1] pass mubi_false 331 1 T2 1 T3 1 T17 1
ins non_zero_bins[1] pass mubi_true 368 1 T3 1 T4 1 T44 1
ins zero pass mubi_false 1973 1 T1 1 T9 1 T4 4
ins zero pass mubi_true 584 1 T1 1 T3 1 T9 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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