Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T38,T97
1	1	Covered	T3,T13,T23

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T15,T7
1	1	Covered	T1,T2,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T19
1	0	Covered	T6,T13,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T9,T19
1	Covered	T6,T13,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T9,T19
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T9,T6
1	Covered	T6,T13,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T6

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T2,T10
AutoCaptGenCnt	143	Covered	T1,T2,T10
AutoCaptReseedCnt	141	Covered	T2,T10,T15
AutoDispatch	125	Covered	T1,T2,T6
AutoFirstAckWait	119	Covered	T1,T2,T6
AutoLoadIns	69	Covered	T1,T2,T9
AutoSendGenCmd	150	Covered	T1,T2,T10
AutoSendReseedCmd	162	Covered	T2,T10,T15
BootDone	98	Covered	T3,T13,T23
BootGenAckWait	90	Covered	T3,T13,T23
BootInsAckWait	80	Covered	T3,T13,T23
BootLoadGen	85	Covered	T3,T13,T23
BootLoadIns	65	Covered	T3,T13,T23
BootLoadUni	102	Covered	T3,T23,T29
BootPulse	94	Covered	T3,T13,T23
BootUniAckWait	107	Covered	T3,T23,T29
Error	188	Covered	T6,T13,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T9,T19
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T10,T15
AutoAckWait->Error	188	Covered	T7,T142,T143
AutoAckWait->Idle	211	Covered	T15,T25,T27
AutoAckWait->RejectCsrngEntropy	188	Covered	T1,T19,T70
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T2,T10
AutoCaptGenCnt->Error	188	Covered	T144,T145
AutoCaptGenCnt->Idle	211	Covered	T27,T138,T135
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T146,T147,T148
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T10,T15
AutoCaptReseedCnt->Error	188	Covered	T149,T150
AutoCaptReseedCnt->Idle	211	Covered	T151,T152,T153
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T26,T154,T155
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T2,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T10,T15
AutoDispatch->Error	188	Covered	T6,T49,T156
AutoDispatch->Idle	138	Covered	T2,T10,T16
AutoDispatch->RejectCsrngEntropy	188	Covered	T157,T158,T159
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T2,T6
AutoFirstAckWait->Error	188	Covered	T50,T160
AutoFirstAckWait->Idle	211	Covered	T73,T161,T162
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T37,T108,T163
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T2,T6
AutoLoadIns->Error	188	Covered	T8,T137,T164
AutoLoadIns->Idle	211	Covered	T1,T9,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T9,T165,T99
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T2,T10
AutoSendGenCmd->Error	188	Covered	T118
AutoSendGenCmd->Idle	211	Covered	T56,T131,T166
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T42,T167,T168
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T10,T15
AutoSendReseedCmd->Error	188	Covered	T169
AutoSendReseedCmd->Idle	211	Covered	T15,T91,T170
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T69,T171,T172
BootDone->BootLoadUni	102	Covered	T3,T23,T29
BootDone->Error	188	Covered	T173
BootDone->Idle	211	Covered	T174,T175,T52
BootDone->RejectCsrngEntropy	188	Covered	T23,T176,T177
BootGenAckWait->BootPulse	94	Covered	T3,T13,T23
BootGenAckWait->Error	188	Covered	T60,T178,T179
BootGenAckWait->Idle	211	Covered	T47,T180,T123
BootGenAckWait->RejectCsrngEntropy	188	Covered	T106,T109,T107
BootInsAckWait->BootLoadGen	85	Covered	T3,T13,T23
BootInsAckWait->Error	188	Covered	T181,T182,T52
BootInsAckWait->Idle	211	Covered	T13,T38,T60
BootInsAckWait->RejectCsrngEntropy	188	Covered	T100,T183,T184
BootLoadGen->BootGenAckWait	90	Covered	T3,T13,T23
BootLoadGen->Error	188	Covered	T46,T140,T51
BootLoadGen->Idle	211	Covered	T97,T127,T139
BootLoadGen->RejectCsrngEntropy	188	Covered	T53,T98,T185
BootLoadIns->BootInsAckWait	80	Covered	T3,T13,T23
BootLoadIns->Error	188	Covered	T14,T47,T186
BootLoadIns->Idle	211	Covered	T187,T188,T189
BootLoadIns->RejectCsrngEntropy	188	Covered	T190,T191,T192
BootLoadUni->BootUniAckWait	107	Covered	T3,T23,T29
BootLoadUni->Error	188	Covered	T116,T122
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T193,T194,T195
BootPulse->BootDone	98	Covered	T3,T13,T23
BootPulse->Error	188	Covered	T13,T196
BootPulse->Idle	211	Covered	T197,T198,T199
BootPulse->RejectCsrngEntropy	188	Covered	T24,T200,T201
BootUniAckWait->Error	188	Covered	T202
BootUniAckWait->Idle	112	Covered	T3,T23,T29
BootUniAckWait->RejectCsrngEntropy	188	Covered	T203,T204,T205
Idle->AutoLoadIns	69	Covered	T1,T2,T9
Idle->BootLoadIns	65	Covered	T3,T13,T23
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T9,T53,T24
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T129,T206,T207
RejectCsrngEntropy->Idle	211	Covered	T1,T9,T19
SWPortMode->Error	188	Covered	T208,T48,T209
SWPortMode->Idle	211	Covered	T4,T5,T20
SWPortMode->RejectCsrngEntropy	188	Covered	T1,T19,T23

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T23
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T23,T29
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T13,T23,T26
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T29
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T29,T34
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T23,T29
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T6
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T6
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T6
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T10,T16
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T10,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T6
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T19
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T13,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T59,T92,T93

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T6,T13,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T9,T19
0	-	-	1	Covered	T1,T9,T6
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	199715722	81586	0	0
FpvSecCmErrorStEscalate_A	199715722	81717	0	0
u_state_regs_A	199685006	199580779	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	81586	0	0
T6	747	310	0	0
T7	0	231	0	0
T8	0	1107	0	0
T10	3468	0	0	0
T13	1163	632	0	0
T14	0	1139	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	592	0	0
T47	0	724	0	0
T53	2192	0	0	0
T59	0	247	0	0
T60	0	880	0	0
T92	0	336	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	81717	0	0
T6	747	311	0	0
T7	0	232	0	0
T8	0	1108	0	0
T10	3468	0	0	0
T13	1163	633	0	0
T14	0	1140	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	593	0	0
T47	0	725	0	0
T53	2192	0	0	0
T59	0	248	0	0
T60	0	881	0	0
T92	0	337	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199685006	199580779	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	565	436	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0