Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T81,T85
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T82,T83,T84
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399094780	662560	0	0
DepthKnown_A	399431444	399222990	0	0
RvalidKnown_A	399431444	399222990	0	0
WreadyKnown_A	399431444	399222990	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	399431444	730341	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399094780	662560	0	0
T1	4270	726	0	0
T2	14156	9721	0	0
T3	8232	0	0	0
T4	19138	0	0	0
T5	6068	0	0	0
T6	312	95	0	0
T7	0	323	0	0
T9	4762	557	0	0
T10	6936	2300	0	0
T15	0	2898	0	0
T16	0	1673	0	0
T19	0	516	0	0
T44	5786	0	0	0
T45	2546	0	0	0
T53	0	508	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399431444	399222990	0	0
T1	4270	4086	0	0
T2	14156	13982	0	0
T3	8232	8126	0	0
T4	19138	18414	0	0
T5	6068	5762	0	0
T6	1494	1236	0	0
T9	4762	4582	0	0
T10	6936	6782	0	0
T44	5786	5592	0	0
T45	2546	2406	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399431444	399222990	0	0
T1	4270	4086	0	0
T2	14156	13982	0	0
T3	8232	8126	0	0
T4	19138	18414	0	0
T5	6068	5762	0	0
T6	1494	1236	0	0
T9	4762	4582	0	0
T10	6936	6782	0	0
T44	5786	5592	0	0
T45	2546	2406	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399431444	399222990	0	0
T1	4270	4086	0	0
T2	14156	13982	0	0
T3	8232	8126	0	0
T4	19138	18414	0	0
T5	6068	5762	0	0
T6	1494	1236	0	0
T9	4762	4582	0	0
T10	6936	6782	0	0
T44	5786	5592	0	0
T45	2546	2406	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	399431444	730341	0	0
T1	4270	726	0	0
T2	14156	9721	0	0
T3	8232	0	0	0
T4	19138	0	0	0
T5	6068	0	0	0
T6	1494	682	0	0
T9	4762	557	0	0
T10	6936	2300	0	0
T13	0	364	0	0
T15	0	2898	0	0
T16	0	1673	0	0
T19	0	516	0	0
T44	5786	0	0	0
T45	2546	0	0	0
T53	0	508	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T43,T32,T86
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T85,T87
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T84,T88,T89
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	199547390	324290	0	0
DepthKnown_A	199715722	199611495	0	0
RvalidKnown_A	199715722	199611495	0	0
WreadyKnown_A	199715722	199611495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	199715722	357935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199547390	324290	0	0
T1	2135	345	0	0
T2	7078	4862	0	0
T3	4116	0	0	0
T4	9569	0	0	0
T5	3034	0	0	0
T6	156	43	0	0
T7	0	133	0	0
T9	2381	270	0	0
T10	3468	1123	0	0
T15	0	1438	0	0
T16	0	826	0	0
T19	0	251	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T53	0	208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	357935	0	0
T1	2135	345	0	0
T2	7078	4862	0	0
T3	4116	0	0	0
T4	9569	0	0	0
T5	3034	0	0	0
T6	747	326	0	0
T9	2381	270	0	0
T10	3468	1123	0	0
T13	0	183	0	0
T15	0	1438	0	0
T16	0	826	0	0
T19	0	251	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T53	0	208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T81,T90
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T82,T83
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	199547390	338270	0	0
DepthKnown_A	199715722	199611495	0	0
RvalidKnown_A	199715722	199611495	0	0
WreadyKnown_A	199715722	199611495	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	199715722	372406	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199547390	338270	0	0
T1	2135	381	0	0
T2	7078	4859	0	0
T3	4116	0	0	0
T4	9569	0	0	0
T5	3034	0	0	0
T6	156	52	0	0
T7	0	190	0	0
T9	2381	287	0	0
T10	3468	1177	0	0
T15	0	1460	0	0
T16	0	847	0	0
T19	0	265	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T53	0	300	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	372406	0	0
T1	2135	381	0	0
T2	7078	4859	0	0
T3	4116	0	0	0
T4	9569	0	0	0
T5	3034	0	0	0
T6	747	356	0	0
T9	2381	287	0	0
T10	3468	1177	0	0
T13	0	181	0	0
T15	0	1460	0	0
T16	0	847	0	0
T19	0	265	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T53	0	300	0	0