Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	688289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5508213

1

T1

8

T2

27

T3

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1639393	1			T1	4		T2	48		T3	27
values[0x0]	2107415	1			T1	8		T2	14		T3	25
values[0x1]	2449694	1			T1	7		T2	14		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5854452

1

T1

10

T2

42

T3

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23921	1			T23	500		T57	1		T24	473
valid_sources[0x01]	24194	1			T23	526		T24	595		T29	4
valid_sources[0x02]	23225	1			T10	1		T23	522		T33	2
valid_sources[0x03]	23491	1			T10	1		T14	1		T23	497
valid_sources[0x04]	24411	1			T10	1		T23	519		T58	1
valid_sources[0x05]	27517	1			T16	1		T23	450		T20	1
valid_sources[0x06]	23062	1			T23	516		T20	1		T17	1
valid_sources[0x07]	23391	1			T14	1		T23	498		T20	1
valid_sources[0x08]	25203	1			T9	3		T23	511		T57	4
valid_sources[0x09]	24911	1			T23	475		T57	1		T33	1
valid_sources[0x0a]	26571	1			T35	6		T23	484		T27	1
valid_sources[0x0b]	25297	1			T23	507		T17	1		T24	618
valid_sources[0x0c]	22247	1			T23	485		T24	47		T94	1
valid_sources[0x0d]	24431	1			T10	1		T14	1		T35	5
valid_sources[0x0e]	22542	1			T35	1		T23	497		T58	1
valid_sources[0x0f]	22739	1			T23	499		T57	3		T24	451
valid_sources[0x10]	24601	1			T3	1		T10	1		T23	498
valid_sources[0x11]	22404	1			T3	1		T23	493		T255	1
valid_sources[0x12]	24066	1			T3	1		T9	1		T16	2
valid_sources[0x13]	22963	1			T23	514		T20	1		T57	1
valid_sources[0x14]	24900	1			T10	1		T16	2		T23	517
valid_sources[0x15]	23015	1			T10	1		T23	494		T27	7
valid_sources[0x16]	25937	1			T14	2		T21	32		T23	521
valid_sources[0x17]	26900	1			T23	503		T19	13		T212	4
valid_sources[0x18]	22942	1			T3	1		T10	1		T23	517
valid_sources[0x19]	24863	1			T23	525		T24	289		T25	132
valid_sources[0x1a]	26053	1			T10	1		T23	494		T20	1
valid_sources[0x1b]	25718	1			T23	513		T24	496		T140	3
valid_sources[0x1c]	24755	1			T9	2		T23	491		T17	3
valid_sources[0x1d]	23963	1			T16	5		T23	493		T20	2
valid_sources[0x1e]	23183	1			T23	495		T20	1		T24	213
valid_sources[0x1f]	24852	1			T23	495		T255	1		T24	676
valid_sources[0x20]	23857	1			T23	520		T24	400		T94	1
valid_sources[0x21]	24052	1			T3	21		T9	1		T10	1
valid_sources[0x22]	23853	1			T23	546		T17	1		T24	554
valid_sources[0x23]	25596	1			T23	512		T20	1		T19	9
valid_sources[0x24]	24070	1			T3	1		T9	1		T10	1
valid_sources[0x25]	23260	1			T16	3		T23	507		T57	2
valid_sources[0x26]	22846	1			T16	2		T23	528		T20	1
valid_sources[0x27]	25163	1			T9	1		T23	525		T20	1
valid_sources[0x28]	24198	1			T23	490		T20	1		T17	2
valid_sources[0x29]	24704	1			T35	5		T23	518		T17	1
valid_sources[0x2a]	24926	1			T9	1		T14	1		T23	505
valid_sources[0x2b]	24342	1			T9	1		T23	500		T255	1
valid_sources[0x2c]	23882	1			T14	3		T23	536		T20	1
valid_sources[0x2d]	23794	1			T23	453		T20	1		T24	395
valid_sources[0x2e]	23683	1			T34	5		T23	500		T57	1
valid_sources[0x2f]	24163	1			T23	480		T17	1		T33	1
valid_sources[0x30]	23949	1			T23	518		T54	33		T27	1
valid_sources[0x31]	23702	1			T9	1		T10	2		T23	507
valid_sources[0x32]	23895	1			T23	497		T20	1		T27	1
valid_sources[0x33]	25346	1			T14	1		T23	467		T24	485
valid_sources[0x34]	23983	1			T23	488		T58	1		T24	444
valid_sources[0x35]	26257	1			T9	1		T23	557		T24	624
valid_sources[0x36]	26577	1			T10	1		T23	500		T54	3
valid_sources[0x37]	24366	1			T3	1		T10	1		T23	489
valid_sources[0x38]	24916	1			T14	2		T23	518		T27	1
valid_sources[0x39]	24555	1			T23	491		T33	1		T24	499
valid_sources[0x3a]	23909	1			T23	507		T20	1		T24	547
valid_sources[0x3b]	24870	1			T9	2		T16	1		T23	475
valid_sources[0x3c]	22884	1			T1	5		T3	2		T9	2
valid_sources[0x3d]	23734	1			T5	8		T10	1		T23	516
valid_sources[0x3e]	23261	1			T23	483		T17	2		T24	151
valid_sources[0x3f]	22791	1			T9	1		T10	1		T23	546
valid_sources[0x40]	24280	1			T42	25		T21	2		T23	489
valid_sources[0x41]	22361	1			T9	2		T23	511		T24	195
valid_sources[0x42]	24466	1			T23	503		T24	338		T25	425
valid_sources[0x43]	24059	1			T23	524		T24	72		T140	2
valid_sources[0x44]	23416	1			T16	2		T23	459		T24	202
valid_sources[0x45]	24544	1			T9	2		T10	2		T23	485
valid_sources[0x46]	23665	1			T3	1		T10	2		T23	521
valid_sources[0x47]	23777	1			T10	1		T23	541		T20	1
valid_sources[0x48]	24326	1			T3	1		T23	479		T27	2
valid_sources[0x49]	24749	1			T23	520		T24	483		T140	7
valid_sources[0x4a]	24297	1			T23	505		T54	1		T57	4
valid_sources[0x4b]	25417	1			T2	1		T10	4		T23	518
valid_sources[0x4c]	22990	1			T16	1		T23	511		T33	2
valid_sources[0x4d]	23745	1			T23	530		T17	1		T27	1
valid_sources[0x4e]	25215	1			T3	1		T23	488		T20	1
valid_sources[0x4f]	24045	1			T10	2		T23	525		T27	1
valid_sources[0x50]	24836	1			T23	491		T57	1		T255	1
valid_sources[0x51]	24601	1			T14	1		T23	525		T20	1
valid_sources[0x52]	24052	1			T23	488		T27	10		T57	2
valid_sources[0x53]	23844	1			T2	1		T23	523		T17	1
valid_sources[0x54]	23851	1			T16	14		T23	548		T28	6
valid_sources[0x55]	25551	1			T3	1		T16	2		T23	530
valid_sources[0x56]	24429	1			T3	1		T23	479		T20	1
valid_sources[0x57]	25025	1			T9	1		T16	6		T23	500
valid_sources[0x58]	26290	1			T10	1		T23	535		T57	1
valid_sources[0x59]	24932	1			T14	1		T23	510		T20	1
valid_sources[0x5a]	23867	1			T3	1		T23	528		T20	1
valid_sources[0x5b]	23167	1			T10	1		T23	533		T24	259
valid_sources[0x5c]	24853	1			T23	526		T24	431		T25	439
valid_sources[0x5d]	23677	1			T2	1		T3	9		T10	1
valid_sources[0x5e]	23996	1			T3	1		T9	1		T23	504
valid_sources[0x5f]	23042	1			T3	1		T9	1		T10	1
valid_sources[0x60]	23976	1			T23	554		T20	1		T24	542
valid_sources[0x61]	25217	1			T3	1		T23	502		T26	7
valid_sources[0x62]	23838	1			T1	3		T3	1		T9	1
valid_sources[0x63]	23561	1			T23	512		T27	2		T212	7
valid_sources[0x64]	23713	1			T35	6		T23	508		T26	2
valid_sources[0x65]	24951	1			T23	500		T26	1		T33	1
valid_sources[0x66]	25826	1			T23	487		T57	1		T24	172
valid_sources[0x67]	26241	1			T9	2		T10	1		T23	544
valid_sources[0x68]	24107	1			T14	1		T23	499		T20	1
valid_sources[0x69]	23227	1			T23	496		T24	685		T140	2
valid_sources[0x6a]	24774	1			T9	1		T23	515		T54	1
valid_sources[0x6b]	23639	1			T23	480		T24	559		T140	3
valid_sources[0x6c]	24461	1			T9	1		T10	1		T35	5
valid_sources[0x6d]	25866	1			T9	2		T10	3		T23	510
valid_sources[0x6e]	26112	1			T3	1		T10	1		T23	535
valid_sources[0x6f]	25197	1			T3	2		T9	2		T10	1
valid_sources[0x70]	25761	1			T23	516		T33	1		T24	677
valid_sources[0x71]	24110	1			T23	495		T33	1		T24	462
valid_sources[0x72]	25090	1			T9	1		T23	519		T17	1
valid_sources[0x73]	23268	1			T10	1		T23	465		T20	1
valid_sources[0x74]	22658	1			T9	1		T22	66		T23	517
valid_sources[0x75]	24020	1			T16	5		T23	498		T19	3
valid_sources[0x76]	23930	1			T16	6		T23	509		T19	2
valid_sources[0x77]	23502	1			T10	1		T23	498		T17	2
valid_sources[0x78]	23791	1			T9	1		T35	1		T23	490
valid_sources[0x79]	22835	1			T10	1		T23	485		T17	2
valid_sources[0x7a]	25397	1			T23	490		T27	1		T24	499
valid_sources[0x7b]	23578	1			T23	505		T20	1		T24	117
valid_sources[0x7c]	24965	1			T14	1		T16	2		T23	502
valid_sources[0x7d]	26547	1			T23	488		T24	424		T94	1
valid_sources[0x7e]	25505	1			T23	462		T20	1		T58	1
valid_sources[0x7f]	23891	1			T9	2		T23	517		T17	1
valid_sources[0x80]	23412	1			T3	1		T9	2		T23	492

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1387750

1

T1

1

T2

8

T3

10

values[0x0]

all_enables

biggest_size

2062615

1

T1

6

T2

11

T3

20

values[0x1]

all_enables

biggest_size

2057848

1

T1

1

T2

8

T3

23