Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2925	1			T9	4		T22	2		T10	3
non_zero_bins[1]	2055	1			T9	1		T10	3		T35	1
zero	9782	1			T1	3		T2	5		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	592	1			T22	1		T23	3		T56	1
uni	3930	1			T22	2		T10	1		T35	3
gen	4675	1			T1	1		T2	3		T3	2
res	869	1			T9	3		T10	2		T16	2
ins	4696	1			T1	2		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9795

1

T2

2

T9

4

T22

6

mubi_true

4967

1

T1

3

T2

3

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

17

1

T2

1

T21

1

T33

1

pass

14745

1

T1

3

T2

4

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	140	1			T56	1		T24	1		T25	5
upd	non_zero_bins[0]	pass	mubi_true	147	1			T24	7		T25	3		T67	1
upd	non_zero_bins[1]	pass	mubi_false	84	1			T23	1		T24	1		T25	2
upd	non_zero_bins[1]	pass	mubi_true	105	1			T25	2		T69	2		T61	1
upd	zero	pass	mubi_false	58	1			T22	1		T23	2		T25	1
upd	zero	pass	mubi_true	58	1			T212	1		T24	1		T25	1
uni	zero	pass	mubi_false	2950	1			T22	2		T10	1		T35	2
uni	zero	pass	mubi_true	980	1			T35	1		T23	13		T254	1
gen	non_zero_bins[0]	pass	mubi_false	513	1			T22	1		T23	6		T20	1
gen	non_zero_bins[0]	pass	mubi_true	557	1			T23	2		T19	1		T255	3
gen	non_zero_bins[1]	pass	mubi_false	373	1			T10	3		T35	1		T16	3
gen	non_zero_bins[1]	pass	mubi_true	426	1			T16	1		T23	3		T20	3
gen	zero	fail	mubi_false	14	1			T2	1		T21	1		T33	1
gen	zero	pass	mubi_false	2055	1			T34	2		T10	1		T14	1
gen	zero	pass	mubi_true	737	1			T1	1		T2	2		T3	2
res	non_zero_bins[0]	pass	mubi_false	199	1			T9	3		T23	2		T17	2
res	non_zero_bins[0]	pass	mubi_true	204	1			T10	2		T23	2		T255	2
res	non_zero_bins[1]	pass	mubi_false	145	1			T23	3		T17	1		T18	1
res	non_zero_bins[1]	pass	mubi_true	138	1			T16	2		T25	2		T52	1
res	zero	fail	mubi_false	3	1			T291	1		T292	1		T293	1
res	zero	pass	mubi_false	111	1			T20	2		T6	1		T24	1
res	zero	pass	mubi_true	69	1			T23	1		T24	1		T69	1
ins	non_zero_bins[0]	pass	mubi_false	612	1			T22	1		T35	1		T23	11
ins	non_zero_bins[0]	pass	mubi_true	553	1			T9	1		T10	1		T23	8
ins	non_zero_bins[1]	pass	mubi_false	393	1			T9	1		T23	2		T18	1
ins	non_zero_bins[1]	pass	mubi_true	391	1			T16	1		T23	1		T24	4
ins	zero	pass	mubi_false	2145	1			T2	1		T22	1		T34	2
ins	zero	pass	mubi_true	602	1			T1	2		T2	1		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded