Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.33	100.00	94.44		94.59	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	94.44		94.59	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T34
1	1	Covered	T1,T3,T22

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T9,T26,T36
1	1	Covered	T2,T3,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T4,T5

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T21
1	Covered	T1,T4,T5

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T21
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	70	94.59
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T9,T10
AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoCaptReseedCnt	141	Covered	T9,T10,T16
AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns	69	Covered	T2,T3,T9
AutoSendGenCmd	150	Covered	T2,T9,T10
AutoSendReseedCmd	162	Covered	T9,T10,T16
BootDone	98	Covered	T1,T22,T34
BootGenAckWait	90	Covered	T1,T22,T34
BootInsAckWait	80	Covered	T1,T3,T22
BootLoadGen	85	Covered	T1,T22,T34
BootLoadIns	65	Covered	T1,T3,T22
BootLoadUni	102	Covered	T22,T35,T27
BootPulse	94	Covered	T1,T22,T34
BootUniAckWait	107	Covered	T22,T35,T27
Error	188	Covered	T1,T4,T5
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T3,T21
SWPortMode	74	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T16
AutoAckWait->Error	188	Covered	T146
AutoAckWait->Idle	211	Covered	T9,T17,T18
AutoAckWait->RejectCsrngEntropy	188	Covered	T2,T21,T26
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T9,T10
AutoCaptGenCnt->Error	188	Covered	T43,T147,T148
AutoCaptGenCnt->Idle	211	Covered	T123,T102
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T135,T75,T149
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T16
AutoCaptReseedCnt->Error	188	Covered	T150,T49,T151
AutoCaptReseedCnt->Idle	211	Covered	T53,T152,T153
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T39,T154,T155
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T16
AutoDispatch->Error	188	Covered	T128,T156
AutoDispatch->Idle	138	Covered	T10,T16,T20
AutoDispatch->RejectCsrngEntropy	188	Covered	T157,T158,T159
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait->Error	188	Covered	T7,T160,T131
AutoFirstAckWait->Idle	211	Covered	T78,T161,T162
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T163,T164,T165
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns->Error	188	Covered	T44,T166,T167
AutoLoadIns->Idle	211	Covered	T3,T21,T57
AutoLoadIns->RejectCsrngEntropy	188	Covered	T168,T169,T170
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T9,T10
AutoSendGenCmd->Error	188	Covered	T118,T171,T172
AutoSendGenCmd->Idle	211	Covered	T18,T129,T104
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T57,T173,T174
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T10,T16
AutoSendReseedCmd->Error	188	Covered	T6,T175
AutoSendReseedCmd->Idle	211	Covered	T9,T176,T177
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T143,T178,T179
BootDone->BootLoadUni	102	Covered	T22,T35,T27
BootDone->Error	188	Covered	T46,T48,T106
BootDone->Idle	211	Covered	T180,T181,T182
BootDone->RejectCsrngEntropy	188	Covered	T38,T64,T183
BootGenAckWait->BootPulse	94	Covered	T1,T22,T34
BootGenAckWait->Error	188	Not Covered
BootGenAckWait->Idle	211	Covered	T34,T97,T184
BootGenAckWait->RejectCsrngEntropy	188	Covered	T54,T139,T185
BootInsAckWait->BootLoadGen	85	Covered	T1,T22,T34
BootInsAckWait->Error	188	Covered	T186,T187,T114
BootInsAckWait->Idle	211	Covered	T1,T121,T46
BootInsAckWait->RejectCsrngEntropy	188	Covered	T3,T36,T76
BootLoadGen->BootGenAckWait	90	Covered	T1,T22,T34
BootLoadGen->Error	188	Covered	T188,T189
BootLoadGen->Idle	211	Covered	T112,T116,T190
BootLoadGen->RejectCsrngEntropy	188	Covered	T62,T191
BootLoadIns->BootInsAckWait	80	Covered	T1,T3,T22
BootLoadIns->Error	188	Covered	T101,T192,T193
BootLoadIns->Idle	211	Covered	T194,T195,T196
BootLoadIns->RejectCsrngEntropy	188	Covered	T27,T197
BootLoadUni->BootUniAckWait	107	Covered	T22,T35,T27
BootLoadUni->Error	188	Covered	T110,T198,T199
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T200,T201,T202
BootPulse->BootDone	98	Covered	T1,T22,T34
BootPulse->Error	188	Covered	T126,T203,T204
BootPulse->Idle	211	Covered	T205,T206,T207
BootPulse->RejectCsrngEntropy	188	Covered	T208
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T22,T35,T27
BootUniAckWait->RejectCsrngEntropy	188	Covered	T141,T142,T209
Idle->AutoLoadIns	69	Covered	T2,T3,T9
Idle->BootLoadIns	65	Covered	T1,T3,T22
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T3,T139,T38
Idle->SWPortMode	74	Covered	T2,T3,T4
RejectCsrngEntropy->Error	188	Covered	T210,T211
RejectCsrngEntropy->Idle	211	Covered	T2,T3,T21
SWPortMode->Error	188	Covered	T5,T14,T59
SWPortMode->Idle	211	Covered	T2,T23,T26
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T21,T26

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T34
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T34
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T34
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T34
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T35,T27
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T34,T27
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T35,T27
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T22,T35,T212
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T22,T35,T27
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T16,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T16
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T16
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T16
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T16
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T58

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T3,T21
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	218283600	86478	0	0
FpvSecCmErrorStEscalate_A	218283600	86612	0	0
u_state_regs_A	218242616	218139292	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	86478	0	0
T1	1873	1084	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1121	0	0
T5	673	332	0	0
T6	0	638	0	0
T7	0	621	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1159	0	0
T15	0	385	0	0
T22	2047	0	0	0
T28	0	1060	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	309	0	0
T59	0	358	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	86612	0	0
T1	1873	1085	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1122	0	0
T5	673	333	0	0
T6	0	639	0	0
T7	0	622	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1160	0	0
T15	0	386	0	0
T22	2047	0	0	0
T28	0	1061	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	310	0	0
T59	0	359	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218242616	218139292	0	0
T1	1699	1559	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1739	1557	0	0
T5	553	362	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0