Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.58	100.00	83.78	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T89,T90
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T83,T84,T91
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	436202582	600262	0	0
DepthKnown_A	436567200	436360552	0	0
RvalidKnown_A	436567200	436360552	0	0
WreadyKnown_A	436567200	436360552	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	436567200	693696	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436202582	600262	0	0
T2	4392	487	0	0
T3	3806	91	0	0
T4	248	0	0	0
T5	230	0	0	0
T9	8488	5746	0	0
T10	9206	7193	0	0
T14	1022	0	0	0
T16	0	1137	0	0
T20	0	9167	0	0
T21	0	978	0	0
T22	4094	0	0	0
T26	0	531	0	0
T34	1746	0	0	0
T36	0	302	0	0
T42	2060	0	0	0
T54	0	305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436567200	436360552	0	0
T1	3746	3466	0	0
T2	4392	4280	0	0
T3	3806	3652	0	0
T4	3892	3528	0	0
T5	1346	964	0	0
T9	8488	8336	0	0
T10	9206	9042	0	0
T22	4094	3912	0	0
T34	1746	1556	0	0
T42	2060	1900	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436567200	436360552	0	0
T1	3746	3466	0	0
T2	4392	4280	0	0
T3	3806	3652	0	0
T4	3892	3528	0	0
T5	1346	964	0	0
T9	8488	8336	0	0
T10	9206	9042	0	0
T22	4094	3912	0	0
T34	1746	1556	0	0
T42	2060	1900	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436567200	436360552	0	0
T1	3746	3466	0	0
T2	4392	4280	0	0
T3	3806	3652	0	0
T4	3892	3528	0	0
T5	1346	964	0	0
T9	8488	8336	0	0
T10	9206	9042	0	0
T22	4094	3912	0	0
T34	1746	1556	0	0
T42	2060	1900	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	436567200	693696	0	0
T1	3746	253	0	0
T2	4392	487	0	0
T3	3806	91	0	0
T4	3892	314	0	0
T5	1346	220	0	0
T9	8488	5746	0	0
T10	9206	7193	0	0
T16	0	1137	0	0
T20	0	9167	0	0
T21	0	978	0	0
T22	4094	0	0	0
T34	1746	0	0	0
T42	2060	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T91,T92,T93
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	218101291	305955	0	0
DepthKnown_A	218283600	218180276	0	0
RvalidKnown_A	218283600	218180276	0	0
WreadyKnown_A	218283600	218180276	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	218283600	352744	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218101291	305955	0	0
T2	2196	242	0	0
T3	1903	50	0	0
T4	124	0	0	0
T5	115	0	0	0
T9	4244	2951	0	0
T10	4603	3637	0	0
T14	511	0	0	0
T16	0	573	0	0
T20	0	4626	0	0
T21	0	503	0	0
T22	2047	0	0	0
T26	0	276	0	0
T34	873	0	0	0
T36	0	206	0	0
T42	1030	0	0	0
T54	0	194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	352744	0	0
T1	1873	124	0	0
T2	2196	242	0	0
T3	1903	50	0	0
T4	1946	150	0	0
T5	673	109	0	0
T9	4244	2951	0	0
T10	4603	3637	0	0
T16	0	573	0	0
T20	0	4626	0	0
T21	0	503	0	0
T22	2047	0	0	0
T34	873	0	0	0
T42	1030	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T33,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T89,T90
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T83,T84
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	218101291	294307	0	0
DepthKnown_A	218283600	218180276	0	0
RvalidKnown_A	218283600	218180276	0	0
WreadyKnown_A	218283600	218180276	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	218283600	340952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218101291	294307	0	0
T2	2196	245	0	0
T3	1903	41	0	0
T4	124	0	0	0
T5	115	0	0	0
T9	4244	2795	0	0
T10	4603	3556	0	0
T14	511	0	0	0
T16	0	564	0	0
T20	0	4541	0	0
T21	0	475	0	0
T22	2047	0	0	0
T26	0	255	0	0
T34	873	0	0	0
T36	0	96	0	0
T42	1030	0	0	0
T54	0	111	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	340952	0	0
T1	1873	129	0	0
T2	2196	245	0	0
T3	1903	41	0	0
T4	1946	164	0	0
T5	673	111	0	0
T9	4244	2795	0	0
T10	4603	3556	0	0
T16	0	564	0	0
T20	0	4541	0	0
T21	0	475	0	0
T22	2047	0	0	0
T34	873	0	0	0
T42	1030	0	0	0