Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	151	1			T3	1		T28	1		T56	1
auto_req_mode	141	1			T9	1		T10	1		T19	1
sw_mode	3076	1			T1	1		T47	1		T43	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

280

1

T43

1

T27

1

T28

1

single

120

1

T3

1

T9

1

T30

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1281	1			T1	1		T3	1		T47	1
auto[2]	33	1			T57	1		T294	1		T295	1
auto[3]	199	1			T9	1		T45	3		T34	1
auto[4]	184	1			T28	1		T296	1		T297	1
auto[5]	100	1			T29	1		T102	6		T298	6
auto[6]	95	1			T27	1		T40	1		T69	1
auto[7]	1476	1			T30	1		T31	1		T39	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[5]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	84	1			T3	1		T56	1		T105	1
auto[1]	auto_req_mode	87	1			T10	1		T19	1		T17	1
auto[1]	sw_mode	1110	1			T1	1		T47	1		T43	1
auto[2]	boot_req_mode	3	1			T294	1		T299	1		T300	1
auto[2]	auto_req_mode	2	1			T301	1		T302	1		-	-
auto[2]	sw_mode	28	1			T57	1		T295	1		T303	4
auto[3]	boot_req_mode	4	1			T304	1		T305	1		T306	1
auto[3]	auto_req_mode	5	1			T9	1		T307	1		T308	1
auto[3]	sw_mode	190	1			T45	3		T34	1		T103	14
auto[4]	boot_req_mode	4	1			T28	1		T296	1		T309	1
auto[4]	auto_req_mode	3	1			T297	1		T310	1		T311	1
auto[4]	sw_mode	177	1			T312	1		T313	15		T314	78
auto[5]	auto_req_mode	7	1			T11	1		T315	1		T316	1
auto[5]	sw_mode	93	1			T29	1		T102	6		T298	6
auto[6]	boot_req_mode	5	1			T40	1		T317	1		T318	1
auto[6]	auto_req_mode	5	1			T37	1		T319	1		T320	1
auto[6]	sw_mode	85	1			T27	1		T69	1		T70	1
auto[7]	boot_req_mode	51	1			T31	1		T33	1		T38	1
auto[7]	auto_req_mode	32	1			T18	1		T20	1		T321	1
auto[7]	sw_mode	1393	1			T30	1		T39	1		T35	1