Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	648937	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5148224

1

T1

27

T2

25

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1541342	1			T1	44		T2	35		T3	128
values[0x0]	1968899	1			T1	17		T2	10		T3	9
values[0x1]	2286920	1			T1	15		T2	15		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	324581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5472580

1

T1

34

T2

37

T3

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21730	1			T3	1		T46	2		T34	1
valid_sources[0x01]	21074	1			T3	2		T16	1		T9	2
valid_sources[0x02]	21308	1			T1	1		T3	1		T10	1
valid_sources[0x03]	22400	1			T1	1		T3	1		T46	1
valid_sources[0x04]	23698	1			T3	2		T4	6		T56	1
valid_sources[0x05]	23486	1			T1	1		T46	5		T57	1
valid_sources[0x06]	22654	1			T46	2		T57	2		T24	662
valid_sources[0x07]	24219	1			T3	1		T8	1		T43	7
valid_sources[0x08]	22553	1			T1	1		T16	1		T56	2
valid_sources[0x09]	20714	1			T3	1		T9	2		T10	1
valid_sources[0x0a]	21735	1			T43	2		T10	1		T46	1
valid_sources[0x0b]	23567	1			T10	1		T46	7		T24	609
valid_sources[0x0c]	22071	1			T3	1		T34	2		T44	1
valid_sources[0x0d]	23507	1			T2	2		T3	1		T10	1
valid_sources[0x0e]	22058	1			T10	1		T46	3		T57	2
valid_sources[0x0f]	21591	1			T2	1		T21	1		T43	2
valid_sources[0x10]	21685	1			T3	1		T10	1		T4	5
valid_sources[0x11]	22661	1			T2	1		T3	1		T4	3
valid_sources[0x12]	21689	1			T1	1		T43	4		T9	4
valid_sources[0x13]	22806	1			T3	1		T24	642		T31	2
valid_sources[0x14]	20278	1			T8	3		T56	1		T34	1
valid_sources[0x15]	22369	1			T1	1		T8	1		T57	2
valid_sources[0x16]	21250	1			T1	1		T2	1		T10	2
valid_sources[0x17]	21227	1			T56	1		T46	1		T57	2
valid_sources[0x18]	23224	1			T2	1		T3	1		T21	1
valid_sources[0x19]	21716	1			T1	2		T3	1		T8	1
valid_sources[0x1a]	22513	1			T2	1		T43	1		T16	2
valid_sources[0x1b]	22133	1			T46	6		T24	621		T92	2
valid_sources[0x1c]	21451	1			T1	2		T16	1		T9	2
valid_sources[0x1d]	21514	1			T3	2		T8	1		T10	1
valid_sources[0x1e]	22274	1			T3	1		T16	1		T10	3
valid_sources[0x1f]	22099	1			T10	1		T24	586		T105	1
valid_sources[0x20]	22062	1			T57	2		T44	1		T24	594
valid_sources[0x21]	21451	1			T3	1		T8	1		T56	1
valid_sources[0x22]	22350	1			T8	1		T43	9		T10	2
valid_sources[0x23]	23764	1			T34	1		T24	632		T31	2
valid_sources[0x24]	21971	1			T2	1		T9	1		T10	1
valid_sources[0x25]	22011	1			T3	1		T9	2		T10	1
valid_sources[0x26]	22188	1			T8	3		T10	1		T46	1
valid_sources[0x27]	22013	1			T3	1		T9	7		T46	3
valid_sources[0x28]	23303	1			T1	1		T3	2		T21	1
valid_sources[0x29]	20834	1			T2	1		T3	1		T21	1
valid_sources[0x2a]	22861	1			T3	1		T46	4		T24	518
valid_sources[0x2b]	22366	1			T56	1		T34	2		T57	1
valid_sources[0x2c]	22646	1			T3	1		T46	4		T24	501
valid_sources[0x2d]	22316	1			T1	1		T3	3		T9	1
valid_sources[0x2e]	22885	1			T5	1		T46	3		T57	1
valid_sources[0x2f]	23611	1			T43	6		T56	2		T34	1
valid_sources[0x30]	23083	1			T3	1		T5	1		T56	1
valid_sources[0x31]	23513	1			T2	1		T10	1		T46	4
valid_sources[0x32]	22886	1			T3	1		T21	1		T23	10
valid_sources[0x33]	23149	1			T3	2		T8	1		T27	1
valid_sources[0x34]	20229	1			T10	1		T56	1		T46	1
valid_sources[0x35]	21274	1			T10	1		T56	1		T34	1
valid_sources[0x36]	21545	1			T1	2		T3	2		T46	3
valid_sources[0x37]	22511	1			T10	2		T34	1		T57	1
valid_sources[0x38]	22891	1			T3	2		T16	31		T46	3
valid_sources[0x39]	23652	1			T2	1		T3	1		T10	1
valid_sources[0x3a]	22116	1			T3	2		T9	1		T56	1
valid_sources[0x3b]	24340	1			T1	1		T3	1		T4	5
valid_sources[0x3c]	24019	1			T16	2		T56	2		T34	1
valid_sources[0x3d]	23007	1			T3	1		T21	2		T46	3
valid_sources[0x3e]	23089	1			T1	1		T3	1		T56	1
valid_sources[0x3f]	21151	1			T1	1		T2	1		T16	1
valid_sources[0x40]	23728	1			T1	1		T10	1		T46	3
valid_sources[0x41]	21712	1			T1	1		T9	1		T46	4
valid_sources[0x42]	22699	1			T1	2		T3	1		T21	8
valid_sources[0x43]	22353	1			T56	3		T57	1		T24	627
valid_sources[0x44]	22576	1			T8	6		T10	1		T4	21
valid_sources[0x45]	22182	1			T1	1		T2	1		T10	1
valid_sources[0x46]	24309	1			T21	1		T46	2		T57	2
valid_sources[0x47]	23053	1			T56	1		T46	2		T24	619
valid_sources[0x48]	22665	1			T3	1		T10	1		T4	3
valid_sources[0x49]	21616	1			T3	1		T10	2		T46	1
valid_sources[0x4a]	23642	1			T44	2		T24	680		T39	2
valid_sources[0x4b]	23242	1			T1	1		T10	2		T5	1
valid_sources[0x4c]	21359	1			T2	2		T3	2		T8	2
valid_sources[0x4d]	21854	1			T3	1		T8	1		T10	1
valid_sources[0x4e]	24530	1			T1	1		T9	1		T4	6
valid_sources[0x4f]	22621	1			T10	1		T46	1		T24	589
valid_sources[0x50]	24737	1			T9	3		T10	1		T46	1
valid_sources[0x51]	21497	1			T2	1		T46	2		T24	601
valid_sources[0x52]	21820	1			T8	1		T10	1		T46	3
valid_sources[0x53]	22326	1			T46	3		T57	1		T44	3
valid_sources[0x54]	22019	1			T9	1		T10	3		T56	3
valid_sources[0x55]	23379	1			T46	2		T34	1		T24	647
valid_sources[0x56]	24087	1			T3	1		T46	4		T57	1
valid_sources[0x57]	24912	1			T2	1		T56	1		T46	1
valid_sources[0x58]	23399	1			T21	1		T43	1		T46	4
valid_sources[0x59]	21604	1			T3	1		T10	1		T5	2
valid_sources[0x5a]	23948	1			T8	4		T10	1		T57	1
valid_sources[0x5b]	21961	1			T3	2		T5	1		T46	2
valid_sources[0x5c]	21274	1			T1	2		T3	2		T8	2
valid_sources[0x5d]	22496	1			T3	2		T46	1		T24	639
valid_sources[0x5e]	21435	1			T3	2		T10	2		T46	2
valid_sources[0x5f]	23578	1			T3	1		T16	1		T46	7
valid_sources[0x60]	24211	1			T24	701		T31	3		T103	4
valid_sources[0x61]	24037	1			T3	1		T43	5		T57	1
valid_sources[0x62]	21265	1			T2	2		T21	1		T56	1
valid_sources[0x63]	21954	1			T3	2		T10	1		T57	1
valid_sources[0x64]	23460	1			T1	1		T21	4		T10	2
valid_sources[0x65]	23379	1			T46	2		T34	1		T57	3
valid_sources[0x66]	23428	1			T1	1		T10	1		T34	1
valid_sources[0x67]	22704	1			T3	1		T43	6		T10	1
valid_sources[0x68]	20588	1			T34	3		T24	575		T35	2
valid_sources[0x69]	23313	1			T1	1		T2	2		T46	3
valid_sources[0x6a]	24433	1			T1	2		T21	1		T9	2
valid_sources[0x6b]	24145	1			T16	1		T10	1		T34	1
valid_sources[0x6c]	22570	1			T1	1		T2	1		T46	3
valid_sources[0x6d]	23031	1			T5	1		T56	1		T24	573
valid_sources[0x6e]	23074	1			T1	1		T3	1		T8	2
valid_sources[0x6f]	21927	1			T9	1		T46	2		T113	2
valid_sources[0x70]	22405	1			T56	1		T46	1		T57	1
valid_sources[0x71]	22905	1			T2	2		T46	2		T24	581
valid_sources[0x72]	23872	1			T3	1		T113	3		T24	581
valid_sources[0x73]	22470	1			T1	1		T10	1		T22	1
valid_sources[0x74]	22455	1			T1	1		T46	2		T24	569
valid_sources[0x75]	21979	1			T24	636		T32	1		T337	1
valid_sources[0x76]	21808	1			T3	2		T16	2		T46	3
valid_sources[0x77]	21521	1			T1	1		T3	2		T16	1
valid_sources[0x78]	22623	1			T2	1		T46	5		T24	557
valid_sources[0x79]	22154	1			T3	1		T10	3		T5	1
valid_sources[0x7a]	21577	1			T1	1		T5	1		T56	1
valid_sources[0x7b]	23090	1			T1	1		T3	1		T46	1
valid_sources[0x7c]	22426	1			T3	1		T21	1		T30	243
valid_sources[0x7d]	23192	1			T1	1		T2	1		T27	12
valid_sources[0x7e]	22752	1			T1	1		T3	1		T8	4
valid_sources[0x7f]	21426	1			T2	1		T3	1		T16	1
valid_sources[0x80]	24398	1			T43	1		T56	1		T24	752

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1299518

1

T1

17

T2

9

T3

3

values[0x0]

all_enables

biggest_size

1926202

1

T1

5

T2

6

T3

8

values[0x1]

all_enables

biggest_size

1922504

1

T1

5

T2

10

T3

17