Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst	100.00	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	22	1			T36	2		T202	2		T325	2
others[1]	26	1			T21	2		T66	2		T77	1
others[2]	32	1			T8	2		T104	2		T156	2
others[3]	40	1			T47	1		T44	2		T113	2
false	3538	1			T1	1		T2	12		T3	2
true	819	1			T8	1		T16	2		T9	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	16	1			T73	2		T78	1		T197	2
others[1]	32	1			T77	1		T326	2		T176	2
others[2]	12	1			T107	2		T247	2		T327	2
others[3]	44	1			T47	1		T108	2		T109	2
false	3751	1			T1	1		T2	9		T3	1
true	622	1			T2	3		T3	1		T21	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	10	1			T328	1		T177	1		T165	1
others[1]	16	1			T68	1		T94	1		T78	1
others[2]	4	1			T110	1		T329	1		T330	1
others[3]	17	1			T47	1		T111	1		T331	1
false	3562	1			T1	1		T2	10		T3	2
true	868	1			T2	2		T21	2		T8	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33	1			T67	2		T174	2		T332	2
others[1]	15	1			T196	2		T333	2		T190	2
others[2]	28	1			T47	1		T16	2		T106	2
others[3]	45	1			T2	2		T91	2		T92	2
false	2004	1			T2	5		T21	5		T8	5
true	2352	1			T1	1		T2	5		T3	2