Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T16,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T85,T89,T90
1	1	0	Not Covered
1	1	1	Covered	T8,T16,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T79,T82,T88
1	0	1	Covered	T8,T16,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T16,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	421739368	1095974	0	0
DepthKnown_A	422123484	421912954	0	0
RvalidKnown_A	422123484	421912954	0	0
WreadyKnown_A	422123484	421912954	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	422123484	1196231	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421739368	1095974	0	0
T4	0	313	0	0
T8	5562	663	0	0
T9	8654	5927	0	0
T10	5236	3198	0	0
T16	3102	57	0	0
T17	0	4299	0	0
T19	0	2478	0	0
T23	3116	0	0	0
T27	4392	0	0	0
T28	4132	0	0	0
T29	8052	0	0	0
T43	7540	0	0	0
T44	0	368	0	0
T47	2620	0	0	0
T91	0	188	0	0
T92	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422123484	421912954	0	0
T1	7818	7446	0	0
T2	4486	4330	0	0
T3	7446	7332	0	0
T8	5562	5380	0	0
T16	3102	2982	0	0
T21	5080	4944	0	0
T23	3116	2950	0	0
T27	4392	4262	0	0
T43	7540	7410	0	0
T47	2620	2506	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422123484	421912954	0	0
T1	7818	7446	0	0
T2	4486	4330	0	0
T3	7446	7332	0	0
T8	5562	5380	0	0
T16	3102	2982	0	0
T21	5080	4944	0	0
T23	3116	2950	0	0
T27	4392	4262	0	0
T43	7540	7410	0	0
T47	2620	2506	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422123484	421912954	0	0
T1	7818	7446	0	0
T2	4486	4330	0	0
T3	7446	7332	0	0
T8	5562	5380	0	0
T16	3102	2982	0	0
T21	5080	4944	0	0
T23	3116	2950	0	0
T27	4392	4262	0	0
T43	7540	7410	0	0
T47	2620	2506	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	422123484	1196231	0	0
T4	0	1510	0	0
T5	0	236	0	0
T8	5562	663	0	0
T9	8654	5927	0	0
T10	5236	3198	0	0
T16	3102	57	0	0
T17	0	4299	0	0
T19	0	2478	0	0
T22	0	299	0	0
T23	3116	0	0	0
T27	4392	0	0	0
T28	4132	0	0	0
T29	8052	0	0	0
T43	7540	0	0	0
T44	0	368	0	0
T47	2620	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T93,T94,T95
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T16,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T85,T96,T97
1	1	0	Not Covered
1	1	1	Covered	T8,T16,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T79,T88,T98
1	0	1	Covered	T8,T16,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T16,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210869684	541870	0	0
DepthKnown_A	211061742	210956477	0	0
RvalidKnown_A	211061742	210956477	0	0
WreadyKnown_A	211061742	210956477	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	211061742	591241	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210869684	541870	0	0
T4	0	92	0	0
T8	2781	332	0	0
T9	4327	2938	0	0
T10	2618	1592	0	0
T16	1551	21	0	0
T17	0	2128	0	0
T19	0	1196	0	0
T23	1558	0	0	0
T27	2196	0	0	0
T28	2066	0	0	0
T29	4026	0	0	0
T43	3770	0	0	0
T44	0	186	0	0
T47	1310	0	0	0
T91	0	44	0	0
T92	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	591241	0	0
T4	0	629	0	0
T5	0	119	0	0
T8	2781	332	0	0
T9	4327	2938	0	0
T10	2618	1592	0	0
T16	1551	21	0	0
T17	0	2128	0	0
T19	0	1196	0	0
T22	0	156	0	0
T23	1558	0	0	0
T27	2196	0	0	0
T28	2066	0	0	0
T29	4026	0	0	0
T43	3770	0	0	0
T44	0	186	0	0
T47	1310	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T16,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T89,T90,T99
1	1	0	Not Covered
1	1	1	Covered	T8,T16,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T82,T100,T101
1	0	1	Covered	T8,T16,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T16,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210869684	554104	0	0
DepthKnown_A	211061742	210956477	0	0
RvalidKnown_A	211061742	210956477	0	0
WreadyKnown_A	211061742	210956477	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	211061742	604990	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210869684	554104	0	0
T4	0	221	0	0
T8	2781	331	0	0
T9	4327	2989	0	0
T10	2618	1606	0	0
T16	1551	36	0	0
T17	0	2171	0	0
T19	0	1282	0	0
T23	1558	0	0	0
T27	2196	0	0	0
T28	2066	0	0	0
T29	4026	0	0	0
T43	3770	0	0	0
T44	0	182	0	0
T47	1310	0	0	0
T91	0	144	0	0
T92	0	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	604990	0	0
T4	0	881	0	0
T5	0	117	0	0
T8	2781	331	0	0
T9	4327	2989	0	0
T10	2618	1606	0	0
T16	1551	36	0	0
T17	0	2171	0	0
T19	0	1282	0	0
T22	0	143	0	0
T23	1558	0	0	0
T27	2196	0	0	0
T28	2066	0	0	0
T29	4026	0	0	0
T43	3770	0	0	0
T44	0	182	0	0
T47	1310	0	0	0