Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	133	1			T31	1		T139	1		T29	1
auto_req_mode	142	1			T8	1		T9	1		T14	1
sw_mode	2950	1			T1	1		T20	1		T24	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

313

1

T1

1

T8

1

T24

1

single

87

1

T20

1

T9

1

T139

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1436	1			T20	1		T9	1		T26	1
auto[2]	100	1			T16	1		T30	1		T291	1
auto[3]	26	1			T223	16		T299	1		T300	1
auto[4]	59	1			T1	1		T301	1		T302	1
auto[5]	117	1			T61	1		T67	1		T303	1
auto[6]	186	1			T24	1		T33	1		T70	1
auto[7]	1301	1			T8	1		T27	11		T41	7

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[6]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	74	1			T31	1		T139	1		T29	1
auto[1]	auto_req_mode	83	1			T9	1		T14	1		T51	1
auto[1]	sw_mode	1279	1			T20	1		T26	1		T49	1
auto[2]	boot_req_mode	3	1			T304	1		T305	1		T306	1
auto[2]	auto_req_mode	2	1			T16	1		T307	1		-	-
auto[2]	sw_mode	95	1			T30	1		T291	1		T308	1
auto[3]	boot_req_mode	3	1			T309	1		T310	1		T311	1
auto[3]	auto_req_mode	4	1			T299	1		T312	1		T313	1
auto[3]	sw_mode	19	1			T223	16		T300	1		T314	1
auto[4]	boot_req_mode	2	1			T315	1		T316	1		-	-
auto[4]	auto_req_mode	4	1			T301	1		T317	1		T318	1
auto[4]	sw_mode	53	1			T1	1		T302	1		T319	1
auto[5]	boot_req_mode	4	1			T320	1		T321	1		T322	1
auto[5]	auto_req_mode	8	1			T61	1		T67	1		T303	1
auto[5]	sw_mode	105	1			T323	51		T324	7		T325	34
auto[6]	boot_req_mode	5	1			T70	1		T326	1		T327	1
auto[6]	sw_mode	181	1			T24	1		T33	1		T71	1
auto[7]	boot_req_mode	42	1			T37	1		T32	1		T328	1
auto[7]	auto_req_mode	41	1			T8	1		T65	1		T62	1
auto[7]	sw_mode	1218	1			T27	11		T41	7		T25	1