Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	686492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5706332

1

T1

17

T2

40

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1675575	1			T1	73		T2	34		T3	4
values[0x0]	2184285	1			T1	8		T2	18		T3	11
values[0x1]	2532964	1			T1	10		T2	25		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	335741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6057083

1

T1

45

T2

45

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21823	1			T24	5		T41	2		T25	1
valid_sources[0x01]	24984	1			T1	1		T18	1		T41	3
valid_sources[0x02]	24791	1			T2	2		T24	4		T41	2
valid_sources[0x03]	25979	1			T1	1		T8	1		T41	1
valid_sources[0x04]	24074	1			T1	2		T2	1		T8	1
valid_sources[0x05]	26524	1			T26	3		T41	1		T25	6
valid_sources[0x06]	23581	1			T8	1		T26	1		T6	70
valid_sources[0x07]	25589	1			T2	1		T18	1		T14	2
valid_sources[0x08]	24624	1			T18	1		T24	3		T41	2
valid_sources[0x09]	23739	1			T2	2		T41	1		T25	3
valid_sources[0x0a]	24763	1			T3	2		T26	2		T41	3
valid_sources[0x0b]	27501	1			T2	1		T18	1		T41	2
valid_sources[0x0c]	26200	1			T18	3		T31	2		T5	2
valid_sources[0x0d]	26574	1			T3	13		T19	5		T41	1
valid_sources[0x0e]	24954	1			T18	1		T41	1		T21	431
valid_sources[0x0f]	26971	1			T1	2		T8	1		T14	1
valid_sources[0x10]	25626	1			T14	1		T27	23		T41	3
valid_sources[0x11]	24893	1			T1	1		T18	1		T21	446
valid_sources[0x12]	25426	1			T1	7		T24	2		T26	1
valid_sources[0x13]	25966	1			T8	1		T20	15		T18	1
valid_sources[0x14]	24882	1			T24	3		T14	1		T41	2
valid_sources[0x15]	27296	1			T24	6		T14	1		T27	10
valid_sources[0x16]	26589	1			T8	1		T18	1		T27	10
valid_sources[0x17]	25049	1			T2	1		T24	2		T26	1
valid_sources[0x18]	23243	1			T26	1		T41	3		T21	547
valid_sources[0x19]	24362	1			T8	2		T14	2		T27	30
valid_sources[0x1a]	25234	1			T18	1		T14	1		T25	1
valid_sources[0x1b]	25582	1			T18	1		T24	2		T41	12
valid_sources[0x1c]	24614	1			T2	1		T24	1		T21	670
valid_sources[0x1d]	27763	1			T1	1		T24	1		T27	34
valid_sources[0x1e]	25485	1			T2	1		T24	1		T41	4
valid_sources[0x1f]	25532	1			T2	8		T14	1		T41	3
valid_sources[0x20]	26510	1			T27	13		T41	2		T25	1
valid_sources[0x21]	24615	1			T26	2		T14	1		T27	16
valid_sources[0x22]	25085	1			T31	2		T21	632		T57	1
valid_sources[0x23]	26328	1			T41	3		T25	1		T21	357
valid_sources[0x24]	22603	1			T8	3		T41	4		T25	2
valid_sources[0x25]	24558	1			T26	1		T41	2		T25	2
valid_sources[0x26]	24234	1			T27	20		T25	1		T21	392
valid_sources[0x27]	25400	1			T26	1		T14	1		T5	3
valid_sources[0x28]	25475	1			T41	8		T21	326		T33	1
valid_sources[0x29]	23735	1			T1	3		T26	1		T27	14
valid_sources[0x2a]	25380	1			T25	2		T21	209		T7	4
valid_sources[0x2b]	24806	1			T2	1		T26	1		T27	32
valid_sources[0x2c]	26287	1			T14	1		T41	1		T25	8
valid_sources[0x2d]	25285	1			T18	1		T26	2		T27	12
valid_sources[0x2e]	23193	1			T27	5		T41	1		T21	647
valid_sources[0x2f]	24358	1			T41	2		T25	1		T21	109
valid_sources[0x30]	24634	1			T24	1		T27	4		T41	3
valid_sources[0x31]	25890	1			T1	1		T24	1		T41	1
valid_sources[0x32]	25955	1			T2	1		T24	3		T26	1
valid_sources[0x33]	25590	1			T8	1		T26	1		T25	2
valid_sources[0x34]	24105	1			T8	1		T27	38		T21	688
valid_sources[0x35]	24360	1			T2	1		T41	3		T25	1
valid_sources[0x36]	23972	1			T8	1		T26	1		T25	4
valid_sources[0x37]	26779	1			T8	2		T18	1		T21	254
valid_sources[0x38]	23323	1			T18	2		T25	2		T21	932
valid_sources[0x39]	24762	1			T26	1		T27	3		T41	3
valid_sources[0x3a]	25559	1			T26	2		T27	8		T41	2
valid_sources[0x3b]	27223	1			T2	1		T21	757		T51	2
valid_sources[0x3c]	24338	1			T24	1		T41	1		T25	1
valid_sources[0x3d]	24120	1			T41	5		T25	1		T21	446
valid_sources[0x3e]	23406	1			T2	1		T18	1		T26	1
valid_sources[0x3f]	23243	1			T2	1		T14	1		T41	1
valid_sources[0x40]	25082	1			T1	3		T2	1		T18	1
valid_sources[0x41]	23803	1			T1	2		T26	1		T14	1
valid_sources[0x42]	23714	1			T19	6		T27	19		T25	1
valid_sources[0x43]	24228	1			T8	1		T18	1		T24	5
valid_sources[0x44]	26005	1			T8	1		T26	1		T25	1
valid_sources[0x45]	26212	1			T41	1		T25	3		T21	1126
valid_sources[0x46]	24583	1			T1	2		T2	1		T26	2
valid_sources[0x47]	24391	1			T18	1		T26	1		T14	1
valid_sources[0x48]	25185	1			T8	1		T26	1		T27	8
valid_sources[0x49]	23744	1			T18	2		T41	1		T25	1
valid_sources[0x4a]	25960	1			T8	1		T18	1		T26	1
valid_sources[0x4b]	24891	1			T2	1		T18	1		T26	1
valid_sources[0x4c]	23861	1			T5	2		T27	6		T41	1
valid_sources[0x4d]	24753	1			T2	1		T14	1		T27	10
valid_sources[0x4e]	25814	1			T2	1		T4	68		T41	3
valid_sources[0x4f]	24708	1			T8	3		T18	2		T27	16
valid_sources[0x50]	24891	1			T1	5		T14	1		T41	5
valid_sources[0x51]	26005	1			T26	2		T41	2		T21	519
valid_sources[0x52]	23933	1			T2	1		T41	6		T21	538
valid_sources[0x53]	24294	1			T24	1		T27	29		T21	790
valid_sources[0x54]	24481	1			T2	1		T8	1		T27	9
valid_sources[0x55]	25801	1			T1	2		T18	1		T26	1
valid_sources[0x56]	25486	1			T1	1		T24	2		T14	1
valid_sources[0x57]	25794	1			T8	1		T41	5		T25	2
valid_sources[0x58]	24952	1			T1	1		T26	1		T14	1
valid_sources[0x59]	23651	1			T18	2		T24	1		T26	1
valid_sources[0x5a]	24327	1			T1	1		T26	1		T41	4
valid_sources[0x5b]	24025	1			T8	1		T27	30		T41	1
valid_sources[0x5c]	23579	1			T2	1		T8	1		T25	3
valid_sources[0x5d]	23766	1			T8	2		T41	1		T25	1
valid_sources[0x5e]	25269	1			T1	1		T18	1		T41	5
valid_sources[0x5f]	26440	1			T18	1		T26	1		T25	1
valid_sources[0x60]	26040	1			T1	2		T26	2		T41	3
valid_sources[0x61]	23921	1			T14	1		T41	2		T25	2
valid_sources[0x62]	25936	1			T26	1		T14	1		T41	5
valid_sources[0x63]	25366	1			T24	1		T41	4		T25	2
valid_sources[0x64]	25085	1			T24	4		T26	1		T14	1
valid_sources[0x65]	25781	1			T2	2		T18	1		T41	4
valid_sources[0x66]	25730	1			T8	1		T26	1		T27	5
valid_sources[0x67]	26483	1			T19	6		T41	3		T21	722
valid_sources[0x68]	23999	1			T8	1		T14	2		T41	2
valid_sources[0x69]	23810	1			T1	1		T14	2		T41	12
valid_sources[0x6a]	24869	1			T8	2		T21	363		T57	1
valid_sources[0x6b]	26766	1			T8	1		T21	337		T130	1
valid_sources[0x6c]	26126	1			T8	1		T24	1		T26	2
valid_sources[0x6d]	24477	1			T2	6		T41	1		T28	2
valid_sources[0x6e]	24254	1			T8	5		T18	1		T26	1
valid_sources[0x6f]	23329	1			T18	1		T27	8		T41	4
valid_sources[0x70]	26277	1			T2	1		T26	1		T5	2
valid_sources[0x71]	26372	1			T8	1		T24	2		T25	1
valid_sources[0x72]	24508	1			T2	1		T8	1		T26	1
valid_sources[0x73]	24468	1			T1	3		T18	1		T24	3
valid_sources[0x74]	28193	1			T8	2		T41	2		T25	1
valid_sources[0x75]	26447	1			T8	1		T14	1		T41	2
valid_sources[0x76]	24245	1			T9	171		T27	19		T21	93
valid_sources[0x77]	24460	1			T20	6		T25	4		T21	670
valid_sources[0x78]	24376	1			T24	1		T27	3		T21	630
valid_sources[0x79]	23491	1			T25	1		T21	197		T51	3
valid_sources[0x7a]	24666	1			T8	1		T24	2		T25	3
valid_sources[0x7b]	25639	1			T18	1		T26	3		T41	3
valid_sources[0x7c]	24919	1			T1	2		T2	1		T8	3
valid_sources[0x7d]	24102	1			T24	1		T26	1		T14	1
valid_sources[0x7e]	25147	1			T27	27		T41	2		T25	2
valid_sources[0x7f]	23136	1			T1	1		T24	1		T14	3
valid_sources[0x80]	25348	1			T26	1		T21	1341		T51	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1435139

1

T1

4

T2

9

T3

3

values[0x0]

all_enables

biggest_size

2139659

1

T1

6

T2

14

T3

7

values[0x1]

all_enables

biggest_size

2131534

1

T1

7

T2

17

T3

4