Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2832	1			T8	2		T20	1		T9	5
non_zero_bins[1]	2021	1			T1	1		T8	2		T9	2
zero	9443	1			T1	3		T2	5		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	561	1			T41	1		T25	1		T21	4
uni	3769	1			T1	1		T8	1		T20	1
gen	4584	1			T1	1		T2	3		T3	2
res	857	1			T1	1		T8	2		T20	1
ins	4525	1			T1	1		T2	2		T3	3

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9345

1

T1

4

T2

2

T3

2

mubi_true

4951

1

T2

3

T3

3

T8

5

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

21

1

T2

1

T135

1

T132

1

pass

14275

1

T1

4

T2

4

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	143	1			T21	1		T30	1		T22	2
upd	non_zero_bins[0]	pass	mubi_true	125	1			T25	1		T21	1		T22	2
upd	non_zero_bins[1]	pass	mubi_false	91	1			T21	2		T130	1		T23	1
upd	non_zero_bins[1]	pass	mubi_true	92	1			T41	1		T130	1		T53	1
upd	zero	pass	mubi_false	63	1			T23	1		T224	1		T286	1
upd	zero	pass	mubi_true	47	1			T22	1		T53	1		T54	1
uni	zero	pass	mubi_false	2781	1			T1	1		T8	1		T20	1
uni	zero	pass	mubi_true	988	1			T24	1		T26	1		T49	1
gen	non_zero_bins[0]	pass	mubi_false	565	1			T8	1		T9	3		T27	1
gen	non_zero_bins[0]	pass	mubi_true	527	1			T20	1		T9	1		T26	1
gen	non_zero_bins[1]	pass	mubi_false	388	1			T1	1		T27	1		T41	1
gen	non_zero_bins[1]	pass	mubi_true	394	1			T24	1		T287	1		T21	2
gen	zero	fail	mubi_false	19	1			T2	1		T135	1		T132	1
gen	zero	pass	mubi_false	1914	1			T3	2		T19	1		T5	1
gen	zero	pass	mubi_true	777	1			T2	2		T8	3		T18	2
res	non_zero_bins[0]	pass	mubi_false	194	1			T130	1		T22	3		T65	2
res	non_zero_bins[0]	pass	mubi_true	199	1			T27	2		T21	3		T15	2
res	non_zero_bins[1]	pass	mubi_false	128	1			T41	1		T21	1		T10	2
res	non_zero_bins[1]	pass	mubi_true	161	1			T8	2		T9	2		T14	1
res	zero	fail	mubi_false	2	1			T288	1		T289	1		-	-
res	zero	pass	mubi_false	78	1			T1	1		T20	1		T134	1
res	zero	pass	mubi_true	95	1			T139	1		T21	1		T23	1
ins	non_zero_bins[0]	pass	mubi_false	546	1			T8	1		T9	1		T24	1
ins	non_zero_bins[0]	pass	mubi_true	533	1			T26	1		T27	1		T287	1
ins	non_zero_bins[1]	pass	mubi_false	380	1			T21	6		T15	1		T16	1
ins	non_zero_bins[1]	pass	mubi_true	387	1			T24	1		T26	1		T14	1
ins	zero	pass	mubi_false	2053	1			T1	1		T2	1		T18	1
ins	zero	pass	mubi_true	626	1			T2	1		T3	3		T20	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded