Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T3,T31,T5
1	1	Covered	T3,T18,T19

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T18,T4,T14
1	1	Covered	T2,T8,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T18,T19
1	0	Covered	T3,T4,T5

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T18,T19
1	Covered	T3,T4,T5

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T18,T19
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T3,T4,T5

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T18

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T8,T9
AutoCaptGenCnt	143	Covered	T2,T8,T9
AutoCaptReseedCnt	141	Covered	T8,T9,T14
AutoDispatch	125	Covered	T2,T8,T9
AutoFirstAckWait	119	Covered	T2,T8,T9
AutoLoadIns	69	Covered	T2,T8,T9
AutoSendGenCmd	150	Covered	T2,T8,T9
AutoSendReseedCmd	162	Covered	T8,T9,T14
BootDone	98	Covered	T3,T19,T31
BootGenAckWait	90	Covered	T3,T18,T19
BootInsAckWait	80	Covered	T3,T18,T19
BootLoadGen	85	Covered	T3,T18,T19
BootLoadIns	65	Covered	T3,T18,T19
BootLoadUni	102	Covered	T19,T139,T63
BootPulse	94	Covered	T3,T19,T31
BootUniAckWait	107	Covered	T19,T139,T63
Error	188	Covered	T3,T4,T5
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T18,T19
SWPortMode	74	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T8,T9,T14
AutoAckWait->Error	188	Covered	T146
AutoAckWait->Idle	211	Covered	T14,T51,T17
AutoAckWait->RejectCsrngEntropy	188	Covered	T2,T134,T132
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T8,T9
AutoCaptGenCnt->Error	188	Covered	T4,T7,T47
AutoCaptGenCnt->Idle	211	Covered	T114,T115,T102
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T147,T148,T149
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T8,T9,T14
AutoCaptReseedCnt->Error	188	Covered	T150,T151,T152
AutoCaptReseedCnt->Idle	211	Covered	T153,T154,T155
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T156,T157,T158
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T8,T9
AutoDispatch->AutoCaptReseedCnt	141	Covered	T8,T9,T14
AutoDispatch->Error	188	Covered	T159,T160
AutoDispatch->Idle	138	Covered	T8,T9,T15
AutoDispatch->RejectCsrngEntropy	188	Covered	T40,T137,T161
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T8,T9
AutoFirstAckWait->Error	188	Covered	T162,T163
AutoFirstAckWait->Idle	211	Covered	T14,T51,T17
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T164,T165,T166
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T8,T9
AutoLoadIns->Error	188	Covered	T167,T168,T169
AutoLoadIns->Idle	211	Covered	T2,T4,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T136,T170,T171
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T8,T9
AutoSendGenCmd->Error	188	Covered	T172,T107
AutoSendGenCmd->Idle	211	Covered	T100,T109,T118
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T173,T141,T174
AutoSendReseedCmd->AutoAckWait	168	Covered	T8,T9,T14
AutoSendReseedCmd->Error	188	Covered	T175
AutoSendReseedCmd->Idle	211	Covered	T176,T177,T178
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T140,T179,T180
BootDone->BootLoadUni	102	Covered	T19,T139,T63
BootDone->Error	188	Covered	T181,T106,T182
BootDone->Idle	211	Covered	T3,T29,T183
BootDone->RejectCsrngEntropy	188	Covered	T28,T34,T184
BootGenAckWait->BootPulse	94	Covered	T3,T19,T31
BootGenAckWait->Error	188	Covered	T13,T185
BootGenAckWait->Idle	211	Covered	T35,T185,T95
BootGenAckWait->RejectCsrngEntropy	188	Covered	T18,T135,T68
BootInsAckWait->BootLoadGen	85	Covered	T3,T18,T19
BootInsAckWait->Error	188	Covered	T3,T45,T113
BootInsAckWait->Idle	211	Covered	T31,T5,T56
BootInsAckWait->RejectCsrngEntropy	188	Covered	T186,T187,T188
BootLoadGen->BootGenAckWait	90	Covered	T3,T18,T19
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T38,T189,T190
BootLoadGen->RejectCsrngEntropy	188	Covered	T191,T192,T193
BootLoadIns->BootInsAckWait	80	Covered	T3,T18,T19
BootLoadIns->Error	188	Covered	T5,T98,T99
BootLoadIns->Idle	211	Covered	T66,T97,T194
BootLoadIns->RejectCsrngEntropy	188	Covered	T59,T195,T196
BootLoadUni->BootUniAckWait	107	Covered	T19,T139,T63
BootLoadUni->Error	188	Covered	T56,T197
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T19,T60,T138
BootPulse->BootDone	98	Covered	T3,T19,T31
BootPulse->Error	188	Covered	T198,T199,T200
BootPulse->Idle	211	Covered	T92,T201,T93
BootPulse->RejectCsrngEntropy	188	Covered	T202,T203,T204
BootUniAckWait->Error	188	Covered	T205,T119,T206
BootUniAckWait->Idle	112	Covered	T19,T139,T132
BootUniAckWait->RejectCsrngEntropy	188	Covered	T63,T133,T73
Idle->AutoLoadIns	69	Covered	T2,T8,T9
Idle->BootLoadIns	65	Covered	T3,T18,T19
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T19,T28,T40
Idle->SWPortMode	74	Covered	T1,T2,T8
RejectCsrngEntropy->Error	188	Covered	T110,T207,T121
RejectCsrngEntropy->Idle	211	Covered	T2,T18,T19
SWPortMode->Error	188	Covered	T58,T42,T43
SWPortMode->Idle	211	Covered	T18,T19,T27
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T18,T63

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T31
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T139,T63
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T19,T31
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T139,T63
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T19,T139,T63
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T139,T63
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T8,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T8,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T8,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T9,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T8,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T14
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T8
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T57,T96

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T3,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T18,T19
0	-	-	1	Covered	T2,T3,T18
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	238053005	83614	0	0
FpvSecCmErrorStEscalate_A	238053005	83742	0	0
u_state_regs_A	238013035	237909978	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	83614	0	0
T3	1165	638	0	0
T4	1401	442	0	0
T5	0	260	0	0
T6	0	335	0	0
T7	0	659	0	0
T8	5050	0	0	0
T9	2991	0	0	0
T13	0	1155	0	0
T14	2380	0	0	0
T18	2288	0	0	0
T19	2064	0	0	0
T20	1889	0	0	0
T24	3641	0	0	0
T26	3038	0	0	0
T56	0	637	0	0
T57	0	538	0	0
T58	0	247	0	0
T96	0	203	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	83742	0	0
T3	1165	639	0	0
T4	1401	443	0	0
T5	0	261	0	0
T6	0	336	0	0
T7	0	660	0	0
T8	5050	0	0	0
T9	2991	0	0	0
T13	0	1156	0	0
T14	2380	0	0	0
T18	2288	0	0	0
T19	2064	0	0	0
T20	1889	0	0	0
T24	3641	0	0	0
T26	3038	0	0	0
T56	0	638	0	0
T57	0	539	0	0
T58	0	248	0	0
T96	0	204	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238013035	237909978	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	987	849	0	0
T4	1103	947	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0