Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T82,T83,T84
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T85,T86
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	475745324	1068708	0	0
DepthKnown_A	476106010	475899896	0	0
RvalidKnown_A	476106010	475899896	0	0
WreadyKnown_A	476106010	475899896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	476106010	1159620	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475745324	1068708	0	0
T2	3782	610	0	0
T3	228	0	0	0
T4	770	292	0	0
T6	0	126	0	0
T8	10100	6650	0	0
T9	5982	3895	0	0
T14	0	2691	0	0
T18	4576	65	0	0
T19	4128	0	0	0
T20	3778	0	0	0
T24	7282	0	0	0
T26	6076	0	0	0
T28	0	566	0	0
T40	0	623	0	0
T63	0	151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476106010	475899896	0	0
T1	5526	5340	0	0
T2	3782	3606	0	0
T3	2330	2054	0	0
T4	2802	2490	0	0
T8	10100	9904	0	0
T9	5982	5832	0	0
T18	4576	4462	0	0
T19	4128	4008	0	0
T20	3778	3644	0	0
T24	7282	7146	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476106010	475899896	0	0
T1	5526	5340	0	0
T2	3782	3606	0	0
T3	2330	2054	0	0
T4	2802	2490	0	0
T8	10100	9904	0	0
T9	5982	5832	0	0
T18	4576	4462	0	0
T19	4128	4008	0	0
T20	3778	3644	0	0
T24	7282	7146	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476106010	475899896	0	0
T1	5526	5340	0	0
T2	3782	3606	0	0
T3	2330	2054	0	0
T4	2802	2490	0	0
T8	10100	9904	0	0
T9	5982	5832	0	0
T18	4576	4462	0	0
T19	4128	4008	0	0
T20	3778	3644	0	0
T24	7282	7146	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	476106010	1159620	0	0
T2	3782	610	0	0
T3	2330	281	0	0
T4	2802	1304	0	0
T5	0	220	0	0
T6	0	3022	0	0
T8	10100	6650	0	0
T9	5982	3895	0	0
T14	0	2691	0	0
T18	4576	65	0	0
T19	4128	0	0	0
T20	3778	0	0	0
T24	7282	0	0	0
T26	6076	0	0	0
T28	0	566	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T16,T88
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T82
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T86,T89
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	237872662	528355	0	0
DepthKnown_A	238053005	237949948	0	0
RvalidKnown_A	238053005	237949948	0	0
WreadyKnown_A	238053005	237949948	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	238053005	573402	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237872662	528355	0	0
T2	1891	294	0	0
T3	114	0	0	0
T4	385	132	0	0
T6	0	34	0	0
T8	5050	3309	0	0
T9	2991	1944	0	0
T14	0	1291	0	0
T18	2288	21	0	0
T19	2064	0	0	0
T20	1889	0	0	0
T24	3641	0	0	0
T26	3038	0	0	0
T28	0	246	0	0
T40	0	308	0	0
T63	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	237949948	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	1165	1027	0	0
T4	1401	1245	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	237949948	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	1165	1027	0	0
T4	1401	1245	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	237949948	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	1165	1027	0	0
T4	1401	1245	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	573402	0	0
T2	1891	294	0	0
T3	1165	143	0	0
T4	1401	589	0	0
T5	0	111	0	0
T6	0	1474	0	0
T8	5050	3309	0	0
T9	2991	1944	0	0
T14	0	1291	0	0
T18	2288	21	0	0
T19	2064	0	0	0
T20	1889	0	0	0
T24	3641	0	0	0
T26	3038	0	0	0
T28	0	246	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T83,T84,T90
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T85,T91
1	0	1	Covered	T2,T3,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	237872662	540353	0	0
DepthKnown_A	238053005	237949948	0	0
RvalidKnown_A	238053005	237949948	0	0
WreadyKnown_A	238053005	237949948	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	238053005	586218	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237872662	540353	0	0
T2	1891	316	0	0
T3	114	0	0	0
T4	385	160	0	0
T6	0	92	0	0
T8	5050	3341	0	0
T9	2991	1951	0	0
T14	0	1400	0	0
T18	2288	44	0	0
T19	2064	0	0	0
T20	1889	0	0	0
T24	3641	0	0	0
T26	3038	0	0	0
T28	0	320	0	0
T40	0	315	0	0
T63	0	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	237949948	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	1165	1027	0	0
T4	1401	1245	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	237949948	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	1165	1027	0	0
T4	1401	1245	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	237949948	0	0
T1	2763	2670	0	0
T2	1891	1803	0	0
T3	1165	1027	0	0
T4	1401	1245	0	0
T8	5050	4952	0	0
T9	2991	2916	0	0
T18	2288	2231	0	0
T19	2064	2004	0	0
T20	1889	1822	0	0
T24	3641	3573	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	238053005	586218	0	0
T2	1891	316	0	0
T3	1165	138	0	0
T4	1401	715	0	0
T5	0	109	0	0
T6	0	1548	0	0
T8	5050	3341	0	0
T9	2991	1951	0	0
T14	0	1400	0	0
T18	2288	44	0	0
T19	2064	0	0	0
T20	1889	0	0	0
T24	3641	0	0	0
T26	3038	0	0	0
T28	0	320	0	0